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SN74AHC373DGV PDF预览

SN74AHC373DGV

更新时间： 2024-11-20 23:06:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路电视光电二极管输出元件
页数 文件大小 规格书
18页 572K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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中文翻译

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SN74AHC373DGV 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：PLASTIC, TVSOP-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.1Is Samacsys：N
系列：AHCJESD-30 代码：R-PDSO-G20
长度：5 mm逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：16.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

SN74AHC373DGV 数据手册

 浏览型号SN74AHC373DGV的Datasheet PDF文件第2页浏览型号SN74AHC373DGV的Datasheet PDF文件第3页浏览型号SN74AHC373DGV的Datasheet PDF文件第4页浏览型号SN74AHC373DGV的Datasheet PDF文件第5页浏览型号SN74AHC373DGV的Datasheet PDF文件第6页浏览型号SN74AHC373DGV的Datasheet PDF文件第7页 
SN54AHC373, SN74AHC373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS235I – OCTOBER 1995 – REVISED JULY 2003  
Operating Range 2-V to 5.5-V V  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
– 1000-V Charged-Device Model (C101)  
SN54AHC373 . . . J OR W PACKAGE  
SN74AHC373 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54AHC373 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
3
2
1 20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
14 6D  
9 10 11 12 13  
GND  
description/ordering information  
The ’AHC373 devices are octal transparent D-type latches designed for 2-V to 5.5-V V  
operation.  
CC  
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs  
are latched at the logic levels of the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
interface or pullup components.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74AHC373N  
SN74AHC373N  
Tube  
SN74AHC373DW  
SN74AHC373DWR  
SN74AHC373NSR  
SN74AHC373DBR  
SN74AHC373PW  
SN74AHC373PWR  
SN74AHC373DGVR  
SNJ54AHC373J  
SOIC – DW  
AHC373  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
AHC373  
HA373  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HA373  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
HA373  
SNJ54AHC373J  
SNJ54AHC373W  
SNJ54AHC373FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHC373W  
SNJ54AHC373FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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