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SN74AHC1GU04DBV PDF预览

SN74AHC1GU04DBV

更新时间: 2024-11-23 22:32:55
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
9页 236K
描述
SINGLE INVERTER GATE

SN74AHC1GU04DBV 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOT-23包装说明:LSSOP, TSOP5/6,.11,37
针数:5Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.18
系列:AHCJESD-30 代码:R-PDSO-G5
长度:2.9 mm负载电容(CL):50 pF
逻辑集成电路类型:INVERTER功能数量:1
输入次数:1端子数量:5
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):12 ns认证状态:Not Qualified
座面最大高度:1.45 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.6 mm
Base Number Matches:1

SN74AHC1GU04DBV 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ ꢃ  
ꢀꢋ ꢁꢈ ꢌ ꢍ ꢋꢁ ꢎꢍꢏ ꢐ ꢍꢏ ꢈ ꢄꢐꢍ  
SCLS343Q− APRIL 1996 − REVISED JUNE 2005  
D
D
D
Operating Range 2-V to 5.5-V V  
Unbuffered Output  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
− 1000-V Charged-Device Model (C101)  
DCK PACKAGE  
(TOP VIEW)  
DBV PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
NC  
V
Y
1
2
3
5
1
2
3
5
NC  
A
V
Y
CC  
CC  
1
2
3
5
4
NC  
A
V
Y
CC  
A
4
GND  
4
GND  
GND  
NC – No internal connection  
See mechanical drawings for dimensions.  
description/ordering information  
The SN74AHC1GU04 contains a single inverter gate. The device performs the Boolean function Y = A. Internal  
circuitry consists of a single-stage inverter that can be used in analog applications, such as crystal oscillators.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
SN74AHC1GU04DBVR  
SN74AHC1GU04DBVT  
SN74AHC1GU04DCKR  
SN74AHC1GU04DCKT  
SOT (SOT-23) − DBV  
AU4_  
−40°C to 85°C  
SOT (SC-70) − DCK  
AD_  
AD_  
SOT (SOT-553) − DRL  
Reel of 4000  
SN74AHC1GU04DRLR  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
The actual top-side marking has one additional character that designates the assembly/test site.  
FUNCTION TABLE  
INPUT  
A
OUTPUT  
Y
H
L
L
H
logic diagram (positive logic)  
2
4
A
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢐꢟ  
Copyright 2005, Texas Instruments Incorporated  
ꢛ ꢟ ꢜ ꢛꢔ ꢕꢩ ꢗꢖ ꢚ ꢢꢢ ꢠꢚ ꢘ ꢚ ꢙ ꢟ ꢛ ꢟ ꢘ ꢜ ꢤ  
ꢚꢘ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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