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SN74AHC16540DGG PDF预览

SN74AHC16540DGG

更新时间： 2024-11-17 23:09:39
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 118K
描述
16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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中文翻译

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SN74AHC16540DGG 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-48针数：48
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.64Is Samacsys：N
其他特性：WITH DUAL OUTPUT ENABLE系列：AHC
JESD-30 代码：R-PDSO-G48长度：12.5 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：12.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：6.1 mm
Base Number Matches：1

SN74AHC16540DGG 数据手册

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SN54AHC16540, SN74AHC16540  
16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS331F – MARCH 1996 – REVISED JANUARY 2000  
SN54AHC16540 . . . WD PACKAGE  
SN74AHC16540 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE1  
1Y1  
1OE2  
1A1  
Operating Range 2-V to 5.5-V V  
CC  
2
3
1Y2  
1A2  
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
4
GND  
1Y3  
GND  
1A3  
5
Flow-Through Architecture Optimizes PCB  
Layout  
6
1Y4  
1A4  
7
V
V
CC  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
8
1Y5  
1Y6  
GND  
1Y7  
1Y8  
2Y1  
2Y2  
GND  
2Y3  
2Y4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
9
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
V
V
CC  
CC  
description  
2Y5  
2Y6  
GND  
2Y7  
2Y8  
2A5  
2A6  
GND  
2A7  
2A8  
These 16-bit buffers and bus drivers provide a  
high-performance bus interface for wide data  
paths.  
The 3-state control gate is a 2-input AND gate with  
active-low inputs so that if either output-enable  
(OE1 or OE2) input is high, all corresponding  
outputs are in the high-impedance state.  
2OE1  
2OE2  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54AHC16540 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74AHC16540 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each 8-bit buffer/driver)  
INPUTS  
OUTPUT  
Y
A
L
OE1  
L
OE2  
L
H
L
L
L
H
X
X
H
X
Z
Z
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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