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SN74AHC16373DGV

更新时间： 2024-11-20 23:09:39
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
12页 226K
描述
16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74AHC16373DGV 数据手册

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SN54AHC16373, SN74AHC16373  
16-BIT TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS329G – MARCH 1996 – REVISED JANUARY 2000  
SN54AHC16373 . . . WD PACKAGE  
SN74AHC16373 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Operating Range 2-V to 5.5-V V  
CC  
2
3
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
4
5
Flow-Through Architecture Optimizes PCB  
Layout  
6
V
V
7
CC  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
8
9
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
V
V
CC  
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
description  
The ’AHC16373 devices are 16-bit transparent  
D-type latches with 3-state outputs designed  
specifically for driving highly capacitive or  
relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,  
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the  
D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
The SN54AHC16373 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74AHC16373 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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