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SN74AHC16373DGGR

更新时间： 2024-11-18 05:24:59
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件PC
页数 文件大小 规格书
12页 226K
描述
16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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中文翻译

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SN74AHC16373DGGR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.51Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：181812
Samacsys Pin Count：48Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Small Outline PackagesSamacsys Footprint Name：DGG (R-PDSO-G48)
Samacsys Released Date：2015-04-13 16:56:21Is Samacsys：N
控制类型：ENABLE LOW/HIGH计数方向：UNIDIRECTIONAL
系列：AHC/VHC/H/U/VJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.008 A湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：2/5.5 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：10.5 ns
传播延迟（tpd）：16.5 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceiver
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：6.1 mmBase Number Matches：1

SN74AHC16373DGGR 数据手册

 浏览型号SN74AHC16373DGGR的Datasheet PDF文件第2页浏览型号SN74AHC16373DGGR的Datasheet PDF文件第3页浏览型号SN74AHC16373DGGR的Datasheet PDF文件第4页浏览型号SN74AHC16373DGGR的Datasheet PDF文件第5页浏览型号SN74AHC16373DGGR的Datasheet PDF文件第6页浏览型号SN74AHC16373DGGR的Datasheet PDF文件第7页 
SN54AHC16373, SN74AHC16373  
16-BIT TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS329G – MARCH 1996 – REVISED JANUARY 2000  
SN54AHC16373 . . . WD PACKAGE  
SN74AHC16373 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Operating Range 2-V to 5.5-V V  
CC  
2
3
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
4
5
Flow-Through Architecture Optimizes PCB  
Layout  
6
V
V
7
CC  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
8
9
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
V
V
CC  
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
description  
The ’AHC16373 devices are 16-bit transparent  
D-type latches with 3-state outputs designed  
specifically for driving highly capacitive or  
relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,  
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the  
D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
The SN54AHC16373 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74AHC16373 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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SN74AHC16373DGGR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHC16373DLR TI

完全替代

 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74AHC16373DGVR TI

完全替代

 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74AHC16373DL TI

完全替代

 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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