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SN74AHC125QPWRG4 PDF预览

SN74AHC125QPWRG4

更新时间: 2024-11-05 11:07:59
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路总线驱动器总线收发器
页数 文件大小 规格书
9页 209K
描述
具有三态输出的 4 通道、2V 至 5.5V 缓冲器 | PW | 14 | -40 to 125

SN74AHC125QPWRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.73控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:AHC/VHC/H/U/V
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
湿度敏感等级:1位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:2/5.5 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:8.5 ns传播延迟(tpd):13 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:4.4 mm
Base Number Matches:1

SN74AHC125QPWRG4 数据手册

 浏览型号SN74AHC125QPWRG4的Datasheet PDF文件第2页浏览型号SN74AHC125QPWRG4的Datasheet PDF文件第3页浏览型号SN74AHC125QPWRG4的Datasheet PDF文件第4页浏览型号SN74AHC125QPWRG4的Datasheet PDF文件第5页浏览型号SN74AHC125QPWRG4的Datasheet PDF文件第6页浏览型号SN74AHC125QPWRG4的Datasheet PDF文件第7页 
SN74AHC125Q  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
SGDS015 – FEBRUARY 2002  
D OR PW PACKAGE  
(TOP VIEW)  
Q Devices Meet Automotive Performance  
Requirements  
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4A  
4Y  
3OE  
3A  
3Y  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Operating Range 2-V to 5.5-V V  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
GND  
8
description  
The SN74AHC125Q is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each  
output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate  
passes the data from the A input to its Y output.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
SOIC – D  
Tape and reel  
Tape and reel  
SN74AHC125QDR  
AHC125Q  
HA125Q  
–40°C to 125°C  
TSSOP – PW  
SN74AHC125QPWR  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AHC125QPWRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHC125QPWR TI

完全替代

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74AHC125PWR TI

类似代替

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC125PW TI

类似代替

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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