SN74AHC125Q

更新时间： 2024-11-04 05:25:03

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
9页	209K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74AHC125Q 数据手册

SN74AHC125Q

QUADRUPLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SGDS015 – FEBRUARY 2002

D OR PW PACKAGE

(TOP VIEW)

Q Devices Meet Automotive Performance

Requirements

Customer-Specific Configuration Control

Can Be Supported Along With

Major-Change Approval

1OE

2OE

4OE

3OE

EPIC (Enhanced-Performance Implanted

CMOS) Process

Operating Range 2-V to 5.5-V V

Latch-Up Performance Exceeds 250 mA Per

JESD 17

GND

description

The SN74AHC125Q is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each

output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate

passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

SOIC – D

Tape and reel

SN74AHC125QDR

AHC125Q

HA125Q

–40°C to 125°C

TSSOP – PW

SN74AHC125QPWR

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

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