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SN74ACT8994FN PDF预览

SN74ACT8994FN

更新时间: 2024-09-28 23:03:11
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路uCs集成电路uPs集成电路监视器
页数 文件大小 规格书
11页 159K
描述
DIGITAL BUS MONITOR IEEE STD 1149.1 JTAG SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER

SN74ACT8994FN 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:PLASTIC, LCC-28针数:28
Reach Compliance Code:not_compliantHTS代码:8542.31.00.01
Factory Lead Time:1 week风险等级:5.66
Is Samacsys:NJESD-30 代码:S-PQCC-J28
长度:11.5062 mm端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Other Microprocessor ICs
最大压摆率:200 mA最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11.5062 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

SN74ACT8994FN 数据手册

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SN74ACT8994  
DIGITAL BUS MONITOR  
IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER  
SCAS196E – JULY 1990 – REVISED DECEMBER 1996  
Member of the Texas Instruments SCOPE  
Family of Testability Products  
Performs Parallel-Signature Analysis (PSA)  
of Data Inputs With User-Definable  
Feedback  
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port and  
Boundary-Scan Architecture  
Data Inputs Are Maskable During PSA  
Operations  
Contains a 1024-Word by 16-Bit  
Random-Access Memory (RAM) to Store  
the States of a Digital Bus  
Cascaded PSA Mode Allows Compression  
of Parallel Data Paths Greater Than 16 Bits  
in Width  
Test Operations Are Synchronous to the  
Test Clock or System Clock(s)  
Direct Memory Access (DMA) Speeds  
Memory and Register File Read/Write  
Operations  
Contains Texas Instruments Event  
Qualification Module for Real-Time System  
Test  
Power-Down Mode When RAM Is Idling  
Reduces Power Dissipation  
Eight Protocols for On-Line Signal  
Monitoring and Test Operations  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
Inputs Are TTL-Voltage Compatible  
Packaged in 28-Pin Plastic Chip Carriers  
FN PACKAGE  
(TOP VIEW)  
4
3 2 1 28 27 26  
5
6
7
8
9
D1  
D0  
D8  
D9  
25  
24  
CLK1  
CLK2  
CLK3  
TMS  
TCK  
23 D10  
22  
21  
20  
19  
D11  
D12  
D13  
D14  
10  
11  
12 13 14 15 16 17 18  
description  
The SN74ACT8994 digital bus monitor (DBM) is a member of the Texas Instruments SCOPE testability  
integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary  
scan to facilitate testing of complex circuit-board assemblies. The DBM is a boundary-scannable device  
designed to monitor and/or store the values of a digital bus up to 16 bits in width. It resides in parallel with the  
bus being monitored.  
Data at the D-input pins can be stored in a scannable random-access memory (RAM). Up to 1024 words of  
16 bits can be stored. A parallel-signature analysis (PSA) can be performed on the data or on the contents of  
memory. The PSA operations use a linear-feedback shift-register technique to compress data into a signature.  
The user can configure the device to mask any combination of data inputs and control the feedback used during  
PSA operations.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE and EPIC are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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