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SN74ACT533PWR PDF预览

SN74ACT533PWR

更新时间： 2023-06-19 15:23:52
品牌 Logo 应用领域
德州仪器 - TI 驱动锁存器总线驱动器总线收发器
页数 文件大小 规格书
6页 100K
描述
具有三态输出的八路透明 D 型锁存器 | PW | 20 | -40 to 85

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中文翻译

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SN74ACT533PWR 数据手册

 浏览型号SN74ACT533PWR的Datasheet PDF文件第2页浏览型号SN74ACT533PWR的Datasheet PDF文件第3页浏览型号SN74ACT533PWR的Datasheet PDF文件第4页浏览型号SN74ACT533PWR的Datasheet PDF文件第5页浏览型号SN74ACT533PWR的Datasheet PDF文件第6页 
SN54ACT533, SN74ACT533  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCAS553B – NOVEMBER 1995 – REVISED JANUARY 2000  
SN54ACT533 . . . J OR W PACKAGE  
SN74ACT533 . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
3-State Inverting Outputs Drive Bus Lines  
Directly  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK) and  
Flatpacks (W), and Standard Plastic (N) and  
Ceramic (J) DIPs  
description  
GND  
The ’ACT533 devices are octal transparent  
D-type latches with 3-state outputs. When the  
latch-enable (LE) input is high, the Q outputs  
follow the complements of the data (D) inputs.  
When LE is taken low, the Q outputs are latched  
at the inverted levels set up at the D inputs.  
SN54ACT533 . . . FK PACKAGE  
(TOP VIEW)  
3
2 1 20 19  
18  
8D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
17 7D  
16  
7Q  
15  
6Q  
14  
6D  
9 10 11 12 13  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN54ACT533 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ACT533 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
L
L
H
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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SN74ACT533PWR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ACT533PW TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
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 		Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SSOP -40 to 85
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 		Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SSOP -40 to 85
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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
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 		ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20
SN74ACT534DWR TI

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 		Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SOIC -40 to 85
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 		ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20
SN74ACT534N TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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