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SN74ACT373PW PDF预览

SN74ACT373PW

更新时间: 2024-11-13 23:03:11
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德州仪器 - TI 锁存器输出元件
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描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN74ACT373PW 数据手册

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SN54ACT373, SN74ACT373  
OCTAL D-TYPE TRANSPARENT LATCHES  
WITH 3-STATE OUTPUTS  
SCAS544D – OCTOBER 1995 – REVISED JANUARY 2000  
SN54ACT373 . . . J OR W PACKAGE  
SN74ACT373 . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
Package Options Include Plastic  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
Small-Outline (DW) Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK) and  
Flatpacks (W), and Standard Plastic (N) and  
Ceramic (J) DIPs  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
description  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
SN54ACT373 . . . FK PACKAGE  
(TOP VIEW)  
The eight latches are D-type transparent latches.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines in bus-organized systems without need for  
interface or pullup components.  
9 10 11 12 13  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN54ACT373 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ACT373 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74ACT373PW 替代型号

型号 品牌 替代类型 描述 数据表
SN74ACT373PWR TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74ACT373PWLE TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74AC373PWR TI

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OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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