SN54ACT1284, SN74ACT1284
7-BIT BUS INTERFACES
WITH 3-STATE OUTPUTS
SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996
SN54ACT1284 . . . J OR W PACKAGE
SN74ACT1284 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
3-State Outputs Directly Drive Bus Lines
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
A1
A2
A3
B1
B2
B3
B4
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
CC
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
A4
GND
GND
A5
A6
A7
CC
V
CC
Designed for the IEEE 1284-I (Level 1 Type)
and IEEE 1284-II (Level 2 Type) Electrical
Specifications
B5
13 B6
12 B7
Package Options Include Plastic
11
DIR
HD
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
DIP (N) Packages, Ceramic Chip Carriers
(FK), Flat (W), and DIP (J) Packages
FK PACKAGE
(TOP VIEW)
description
3
2
1 20 19
18
The ’ACT1284 are designed for asynchronous
two-way communication between data buses.
The control function minimizes external timing
requirements.
B3
B4
V
A4
GND
GND
A5
4
5
6
7
8
17
16
15
14
CC
V
CC
B5
A6
The devices allow data transmission in either the
A-to-B or the B-to-A direction for bits 1, 2, 3, and
4, depending on the logic level at the
direction-control (DIR) input. Bits 5, 6, and 7,
however, always transmit in the A-to-B direction.
9 10 11 12 13
The output drive for each mode is determined by the high drive (HD) control pin. When HD is high, the high drive
is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the
drive requirements as specified in the IEEE 1284-I (level 1 type) and the IEEE 1284-II (level 2 type) parallel
peripheral-interface specification.
The SN54ACT1284 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ACT1284 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
MODE
DIR
HD
Open drain
Totem pole
Totem pole
Open drain
Totem pole
A to B: Bits 5, 6, 7
B to A: Bits 1, 2, 3, 4
L
L
L
H
H
H
L
B to A: Bits 1, 2, 3, 4 and A to B: Bits 5, 6, 7
A to B: Bits 1, 2, 3, 4, 5, 6, 7
A to B: Bits 1, 2, 3, 4, 5, 6, 7
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
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