ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢃꢈ ꢉꢊ
ꢋꢉꢌ ꢍꢁ ꢎꢉ ꢏ ꢆꢉ ꢏ
SCAS781 − OCTOBER 2004
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
Inputs Accept Voltages to 5.5 V
Max t of 8.5 ns at 5 V
pd
Inputs Are TTL-Voltage Compatible
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D PACKAGE
(TOP VIEW)
D
D
D
Enhanced Product-Change Notification
†
Qualification Pedigree
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1Y
2A
2Y
3A
V
CC
4.5-V to 5.5-V V
Operation
CC
6A
6Y
5A
5Y
4A
4Y
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
3Y
GND
8
description/ordering information
The SN74ACT04 contains six independent inverters. The device performs the Boolean function Y = A.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
−40°C to 85°C
SOIC − D
Tape and reel SN74ACT04IDREP
SACT04IEP
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram, each inverter (positive logic)
A
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
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