5秒后页面跳转
SN74AC74N PDF预览

SN74AC74N

更新时间: 2024-02-02 00:44:58
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
7页 113K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SN74AC74N 数据手册

 浏览型号SN74AC74N的Datasheet PDF文件第2页浏览型号SN74AC74N的Datasheet PDF文件第3页浏览型号SN74AC74N的Datasheet PDF文件第4页浏览型号SN74AC74N的Datasheet PDF文件第5页浏览型号SN74AC74N的Datasheet PDF文件第6页浏览型号SN74AC74N的Datasheet PDF文件第7页 
SN54AC74, SN74AC74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996  
SN54AC74 . . . J OR W PACKAGE  
SN74AC74 . . . D, DB, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK), Flat  
(W), and DIP (J,N) Packages  
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1CLK  
1PRE  
1Q  
2CLK  
2PRE  
2Q  
description  
1Q  
GND  
2Q  
8
The ’AC74 are dual positive-edge-triggered  
D-type flip-flops.  
Alowlevelatthepreset(PRE)orclear(CLR)input  
sets or resets the outputs, regardless of the levels  
of the other inputs. When PRE and CLR are  
inactive (high), data at the data (D) input meeting  
the setup-time requirements is transferred to the  
outputs on the positive-going edge of the clock  
pulse. Clock triggering occurs at a voltage level  
and is not directly related to the rise time of the  
clock pulse. Following the hold-time interval, data  
at D can be changed without affecting the levels  
at the outputs.  
SN54AC74 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2D  
1CLK  
NC  
4
5
6
7
8
NC  
17  
16  
15  
14  
2CLK  
NC  
1PRE  
NC  
2PRE  
1Q  
9 10 11 12 13  
The SN54AC74 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74AC74 is characterized for  
operation from –40°C to 85°C.  
NC – No internal connection  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
CLR  
PRE  
L
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
H
L
L
X
H
H
H
H
H
H
L
L
H
H
H
L
X
Q
Q
0
0
This configuration is unstable; that is, it does not  
persist when either PRE or CLR returns to its  
inactive (high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AC74N 替代型号

型号 品牌 替代类型 描述 数据表
SN74AC74NE4 TI

类似代替

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74HC74NSR TI

类似代替

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

与SN74AC74N相关器件

型号 品牌 获取价格 描述 数据表
SN74AC74NE4 TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AC74NSR TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AC74NSRE4 ROCHESTER

获取价格

D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS
SN74AC74NSRE4 TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AC74NSRG4 ROCHESTER

获取价格

D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS
SN74AC74NSRG4 TI

获取价格

AC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN,
SN74AC74PW TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AC74PWE4 TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AC74PWE4 ROCHESTER

获取价格

D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS
SN74AC74PWG4 TI

获取价格

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-TSSOP -40 to 85