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SN74AC573DWR PDF预览

SN74AC573DWR

更新时间: 2024-11-08 05:04:55
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
13页 383K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN74AC573DWR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.65其他特性:BROADSIDE VERSION OF 373
控制类型:ENABLE LOW计数方向:UNIDIRECTIONAL
系列:ACJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TR
峰值回流温度(摄氏度):260电源:3.3/5 V
最大电源电流(ICC):0.04 mAProp。Delay @ Nom-Sup:15 ns
传播延迟(tpd):15 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

SN74AC573DWR 数据手册

 浏览型号SN74AC573DWR的Datasheet PDF文件第2页浏览型号SN74AC573DWR的Datasheet PDF文件第3页浏览型号SN74AC573DWR的Datasheet PDF文件第4页浏览型号SN74AC573DWR的Datasheet PDF文件第5页浏览型号SN74AC573DWR的Datasheet PDF文件第6页浏览型号SN74AC573DWR的Datasheet PDF文件第7页 
ꢉ ꢅꢊꢄꢋ ꢌꢍꢊ ꢎꢏ ꢐ ꢊ ꢑꢄꢁꢀ ꢏꢄꢑꢐ ꢁꢊ ꢋꢄꢊꢅ ꢒ ꢐ  
SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003  
SN54AC573 . . . J OR W PACKAGE  
SN74AC573 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
2-V to 6-V V  
Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 9 ns at 5 V  
pd  
3-State Outputs Drive Bus Lines Directly  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
LE  
description/ordering information  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
The eight latches are D-type transparent latches.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D Inputs.  
SN54AC573 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal  
logic state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines in a bus-organized system without need for  
interface or pullup components.  
3
2
1
20 19  
18  
2Q  
3Q  
4Q  
5Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14 6Q  
9 10 11 12 13  
OE does not affect the internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AC573N  
SN74AC573N  
Tube  
SN74AC573DW  
SN74AC573DWR  
SN74AC573NSR  
SN74AC573DBR  
SN74AC573PW  
SN74AC573PWR  
SNJ54AC573J  
SOIC − DW  
AC573  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AC573  
AC573  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
AC573  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC573J  
SNJ54AC573W  
SNJ54AC573FK  
Tube  
SNJ54AC573W  
SNJ54AC573FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢕ ꢁ ꢋꢐꢀꢀ ꢉ ꢊꢒ ꢐꢑꢓ ꢔꢀ ꢐ ꢁ ꢉꢊꢐꢌ ꢖꢗ ꢘꢙ ꢚꢛꢜ ꢝꢞꢟ ꢠꢖ ꢜꢛ ꢠꢖꢡ ꢘꢠꢙ ꢏꢑ ꢉ ꢌ ꢕ ꢅꢊ ꢔꢉ ꢁ  
ꢤꢡ ꢣ ꢡ ꢞ ꢟ ꢖ ꢟ ꢣ ꢙ ꢧ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AC573DWR 替代型号

型号 品牌 替代类型 描述 数据表
CD74AC573M TI

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