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SN74AC563DWE4 PDF预览

SN74AC563DWE4

更新时间: 2024-11-08 22:14:19
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
13页 391K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN74AC563DWE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.47Is Samacsys:N
其他特性:BROADSIDE VERSION OF 533系列:AC
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.012 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:3.3/5 VProp。Delay @ Nom-Sup:15 ns
传播延迟(tpd):15 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

SN74AC563DWE4 数据手册

 浏览型号SN74AC563DWE4的Datasheet PDF文件第2页浏览型号SN74AC563DWE4的Datasheet PDF文件第3页浏览型号SN74AC563DWE4的Datasheet PDF文件第4页浏览型号SN74AC563DWE4的Datasheet PDF文件第5页浏览型号SN74AC563DWE4的Datasheet PDF文件第6页浏览型号SN74AC563DWE4的Datasheet PDF文件第7页 
ꢊ ꢅꢋꢄꢌ ꢍꢎꢋ ꢏꢐ ꢑ ꢋ ꢒꢄꢁꢀ ꢐꢄꢒꢑ ꢁꢋ ꢌꢄꢋꢅ ꢓ ꢑ  
ꢔ ꢕꢋ ꢓ ꢇ ꢎꢀꢋꢄꢋ ꢑ ꢊ ꢖꢋ ꢐꢖ ꢋ  
SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003  
SN54AC563 . . . J OR W PACKAGE  
SN74AC563 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
2-V to 6-V V  
Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 9 ns at 5 V  
pd  
3-State Inverting Outputs Drive Bus Lines  
Directly  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
LE  
D
Full Parallel Access for Loading  
D
Flow-Through Architecture to Optimize  
PCB Layout  
description/ordering information  
The ’AC563 devices are octal D-type transparent  
latches with 3-state outputs. When the  
latch-enable (LE) input is high, the Q outputs  
follow the complements of the data (D) inputs.  
When LE is taken low, the Q outputs are latched  
at the inverse logic levels set up at the D inputs.  
GND  
SN54AC563 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
3
2
1
20 19  
18  
3D  
4D  
5D  
6D  
7D  
2Q  
17 3Q  
4
5
6
7
8
16  
15  
14  
4Q  
5Q  
6Q  
9 10 11 12 13  
OE does not affect internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AC563N  
SN74AC563N  
Tube  
SN74AC563DW  
SN74AC563DWR  
SN74AC563NSR  
SN74AC563DBR  
SN74AC563PW  
SN74AC563PWR  
SNJ54AC563J  
SOIC − DW  
AC563  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AC563  
AC563  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
AC563  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC563J  
SNJ54AC563W  
SNJ54AC563FK  
Tube  
SNJ54AC563W  
SNJ54AC563FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢖ ꢁ ꢌꢑꢀꢀ ꢊ ꢋꢓ ꢑꢒꢔ ꢕꢀ ꢑ ꢁ ꢊꢋꢑꢍ ꢗꢘ ꢙꢚ ꢛꢜꢝ ꢞꢟꢠ ꢡꢗ ꢝꢜ ꢡꢗꢢ ꢙꢡꢚ ꢐꢒ ꢊ ꢍ ꢖ ꢅꢋ ꢕꢊ ꢁ  
ꢥꢢ ꢤ ꢢ ꢟ ꢠ ꢗ ꢠ ꢤ ꢚ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AC563DWE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AC563DWRE4 TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74AC563DWR TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74AC563DW TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

与SN74AC563DWE4相关器件

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AC SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20
SN74AC563DWR TI

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SN74AC563DWRE4 TI

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SN74AC563DWRG4 ROCHESTER

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SN74AC563N TI

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OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74AC563NE4 ROCHESTER

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Bus Driver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDIP20, ROHS COMPLIANT, PLAST
SN74AC563NE4 TI

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OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74AC563NSR TI

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OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74AC563NSRE4 TI

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OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74AC563PW TI

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OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS