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SN74AC533DBLE PDF预览

SN74AC533DBLE

更新时间： 2024-11-18 05:04:55
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
16页 445K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74AC533DBLE 数据手册

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SCAS555C − NOVEMBER 1995 − REVISED OCTOBER 2003  
SN54AC533 . . . J OR W PACKAGE  
SN74AC533 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
2-V to 6-V V  
Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 10.5 ns at 5 V  
pd  
3-State Inverting Outputs Drive Bus Lines  
Directly  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
D
Full Parallel Access for Loading  
description/ordering information  
The ’AC533 devices are octal transparent D-type  
latches with 3-state outputs. When the  
latch-enable (LE) input is high, the Q outputs  
follow the complements of the data (D) inputs.  
When LE is taken low, the Q outputs are latched  
at the inverse logic levels set up at the D inputs.  
GND  
SN54AC533 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
3
2 1 20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
OE does not affect the internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AC533N  
SN74AC533N  
Tube  
SN74AC533DW  
SN74AC533DWR  
SN74AC533NSR  
SN74AC533DBR  
SN74AC533PW  
SN74AC533PWR  
SNJ54AC533J  
SOIC − DW  
AC533  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AC533  
AC533  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
AC533  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC533J  
SNJ54AC533W  
SNJ54AC533FK  
Tube  
SNJ54AC533W  
SNJ54AC533FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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