5秒后页面跳转
SN74AC373PWLE PDF预览

SN74AC373PWLE

更新时间: 2024-11-15 05:04:55
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
19页 590K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN74AC373PWLE 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.26系列:AC
JESD-30 代码:R-PDSO-G20长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.012 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 VProp。Delay @ Nom-Sup:15 ns
传播延迟(tpd):15 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm

SN74AC373PWLE 数据手册

 浏览型号SN74AC373PWLE的Datasheet PDF文件第2页浏览型号SN74AC373PWLE的Datasheet PDF文件第3页浏览型号SN74AC373PWLE的Datasheet PDF文件第4页浏览型号SN74AC373PWLE的Datasheet PDF文件第5页浏览型号SN74AC373PWLE的Datasheet PDF文件第6页浏览型号SN74AC373PWLE的Datasheet PDF文件第7页 
ꢉ ꢅꢊꢄꢋ ꢌꢍꢊ ꢎꢏ ꢐ ꢊ ꢑꢄꢁꢀ ꢏꢄꢑꢐ ꢁꢊ ꢋꢄꢊꢅ ꢒ ꢐ  
ꢓ ꢔꢊ ꢒ ꢆ ꢍꢀꢊꢄꢊ ꢐ ꢉ ꢕꢊ ꢏꢕ ꢊ  
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003  
SN54AC373 . . . J OR W PACKAGE  
SN74AC373 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
2-V to 6-V V  
Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 9.5 ns at 5 V  
pd  
3-State Noninverting Outputs Drive Bus  
Lines Directly  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
D
Full Parallel Access for Loading  
description/ordering information  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
SN54AC373 . . . FK PACKAGE  
(TOP VIEW)  
The eight latches are D-type transparent latches.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
6D  
4
5
6
7
8
17  
16  
15  
14  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines in bus-organized systems without need for  
interface or pullup components.  
9 10 11 12 13  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AC373N  
SN74AC373N  
Tube  
SN74AC373DW  
SN74AC373DWR  
SN74AC373NSR  
SN74AC373DBR  
SN74AC373PW  
SN74AC373PWR  
SNJ54AC373J  
SOIC − DW  
AC373  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AC373  
AC373  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
AC373  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC373J  
SNJ54AC373W  
SNJ54AC373FK  
Tube  
SNJ54AC373W  
SNJ54AC373FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢉ ꢗ ꢢ ꢚ ꢙꢥ ꢠꢟ ꢝꢞ ꢟꢙ ꢛꢢ ꢤꢖ ꢜꢗ ꢝ ꢝꢙ ꢬꢔ ꢋꢍ ꢏꢑ ꢭ ꢍꢆꢮꢂ ꢆꢂꢈ ꢜꢤꢤ ꢢꢜ ꢚ ꢜ ꢛꢡ ꢝꢡꢚ ꢞ ꢜ ꢚ ꢡ ꢝꢡ ꢞꢝꢡ ꢥ  
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
ꢠ ꢗꢤ ꢡꢞꢞ ꢙ ꢝꢧꢡ ꢚ ꢩꢖ ꢞꢡ ꢗ ꢙꢝꢡ ꢥꢦ ꢉ ꢗ ꢜꢤ ꢤ ꢙ ꢝꢧꢡ ꢚ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢞ ꢈ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙ ꢗ  
ꢛꢡ  
ꢡꢚ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AC373PWLE 替代型号

型号 品牌 替代类型 描述 数据表
SN74AC373PWR TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74AC373PW TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
MC74ACT373DTR2G ONSEMI

类似代替

Octal Transparent Latch with 3−State Outputs

与SN74AC373PWLE相关器件

型号 品牌 获取价格 描述 数据表
SN74AC373PWR TI

获取价格

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74AC373PWRE4 TI

获取价格

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74AC374 TI

获取价格

OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS
SN74AC374DB TI

获取价格

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AC374DBLE TI

获取价格

OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS
SN74AC374DBR TI

获取价格

OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS
SN74AC374DBRE4 TI

获取价格

OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS
SN74AC374DBRG4 TI

获取价格

OCTAL D-TYPE EDGE-TRIGGERED FLIP- FLOPS WITH 3-STATE OUTPUTS
SN74AC374DW TI

获取价格

OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS
SN74AC374DWE4 TI

获取价格

OCTAL D-TYPE EDGE-TRIGGERED FLIP- FLOPS WITH 3-STATE OUTPUTS