SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540B – OCTOBER 1995 – REVISED JUNE 1996
SN54AC373 . . . J OR W PACKAGE
SN74AC373 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
3-State Noninverting Outputs Drive Bus
Lines Directly
Full Parallel Access for Loading
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
Package Options Include Plastic
Small-Outline (DW) Shrink Small-Outline
(DB) and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
GND
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
SN54AC373 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
2D
2Q
3Q
3D
4D
8D
7D
7Q
6Q
6D
4
5
6
7
8
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
17
16
15
14
9 10 11 12 13
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the high-
impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The
high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems
without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54AC373 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AC373 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265