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SN74AC11109D PDF预览

SN74AC11109D

更新时间: 2024-11-01 20:01:43
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
7页 95K
描述
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SO-16

SN74AC11109D 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:AC
JESD-30 代码:R-PDSO-G16长度:9.9 mm
逻辑集成电路类型:J-KBAR FLIP-FLOP位数:2
功能数量:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):12.7 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:70 MHz
Base Number Matches:1

SN74AC11109D 数据手册

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ꢀ ꢁ ꢂꢃꢄꢄꢄ ꢅ ꢆ ꢇꢈ ꢉ ꢁꢂ ꢃꢄꢄꢄꢅ ꢆ  
ꢊꢋꢂ ꢌ ꢍ ꢎꢏ ꢐꢑ ꢒꢓ ꢔ ꢓꢕꢖ ꢎꢖꢊꢗ ꢖꢎꢔ ꢘꢓ ꢗ ꢗꢖ ꢘꢖꢊ ꢙ ꢌ ꢓꢐ ꢎ ꢙꢌꢑ ꢐ ꢒ  
ꢚ ꢓꢔ ꢛꢈ ꢃꢌꢖ ꢂꢘꢈꢂꢜꢊ ꢈꢐ ꢘ ꢖꢒ ꢖ ꢔ  
SCAS450 − MARCH 1987 − REVISED APRIL 1993  
54AC11109 . . . J PACKAGE  
74AC11109 . . . D OR N PACKAGE  
(TOP VIEW)  
Flow-Through Architecture Optimizes  
PCB Layout  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
1PRE  
1Q  
1Q  
GND  
2Q  
2Q  
2PRE  
2CLK  
1CLK  
1K  
1J  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
EPIC(Enhanced-Performance Implanted  
CMOS) 1-µm Process  
500-mA Typical Latch-Up Immunity  
at 125°C  
1CLR  
V
CC  
2CLR  
2J  
2K  
ESD Protection Exceeds 2000 V,  
MIL STD-883C Method 3015  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
54AC11109 . . . FK PACKAGE  
(TOP VIEW)  
description  
These devices contain two independent J-K  
positive-edge-triggered flip-flops. A low level at  
the preset (PRE) or clear (CLR) inputs sets or  
resets the outputs regardless of the levels of the  
other inputs. When preset and clear are inactive  
(high), data at the J and K inputs meeting the setup  
time requirements are transferred to the outputs  
on the positive-going edge of the clock pulse.  
Clock triggering occurs at a voltage level and is not  
directly related to the rise time of the clock pulse.  
Following the hold time interval, data at the J and  
K inputs may be changed without affecting the  
levels at the outputs. These versatile flip-flops can  
perform as toggle flip-flops by grounding K and  
tying J high. They also can perform as D-type  
flip-flops by tying the J and K inputs together.  
3
2
1
20 19  
18  
2J  
17 2K  
1K  
4
5
6
7
8
1CLK  
NC  
16  
15  
14  
NC  
2CLK  
2PRE  
1PRE  
1Q  
9 10 11 12 13  
NC − No internal connection  
The 54AC11109 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
74AC11109 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUTS  
PRE  
L
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
CLR  
H
H
L
X
H
H
L
L
X
H
H
H
L
H
H
H
H
L
L
Toggle  
H
H
H
H
X
Q
Q
0
0
H
H
H
X
H
L
H
H
L
Q
Q
0
0
This configuration is nonstable; that is, it will not persist when  
either PRE or CLR returns to its inactive (high) level.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢔꢪ  
Copyright 1993, Texas Instruments Incorporated  
ꢦ ꢪ ꢧ ꢦꢟ ꢠꢴ ꢢꢡ ꢥ ꢭꢭ ꢫꢥ ꢣ ꢥ ꢤ ꢪ ꢦ ꢪ ꢣ ꢧ ꢯ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  

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