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SN74ABTH245PW PDF预览

SN74ABTH245PW

更新时间： 2024-11-27 23:06:15
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
7页 98K
描述
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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中文翻译

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SN74ABTH245PW 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：unknown风险等级：5.57
其他特性：WITH DIRECTION CONTROL系列：ABT
JESD-30 代码：R-PDSO-G20长度：6.5 mm
逻辑集成电路类型：BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：3.9 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：4.4 mmBase Number Matches：1

SN74ABTH245PW 数据手册

 浏览型号SN74ABTH245PW的Datasheet PDF文件第2页浏览型号SN74ABTH245PW的Datasheet PDF文件第3页浏览型号SN74ABTH245PW的Datasheet PDF文件第4页浏览型号SN74ABTH245PW的Datasheet PDF文件第5页浏览型号SN74ABTH245PW的Datasheet PDF文件第6页浏览型号SN74ABTH245PW的Datasheet PDF文件第7页 
SN54ABTH245, SN74ABTH245  
OCTAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999  
SN54ABTH245 . . . J OR W PACKAGE  
SN74ABTH245 . . . DB, DGV, DW, N, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
DIR  
A1  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
CC  
Typical V  
(Output Ground Bounce) < 1 V  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
OLP  
at V  
= 5 V, T = 25°C  
A2  
CC  
A
A3  
I
and Power-Up 3-State Support Hot  
off  
A4  
Insertion  
A5  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
A6  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
A7  
A8  
GND  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Thin Very Small-Outline (DGV) Packages,  
Ceramic Chip Carriers (FK), Plastic (N) and  
Ceramic (J) DIPs, and Ceramic Flat (W)  
Package  
SN54ABTH245 . . . FK PACKAGE  
(TOP VIEW)  
3
2 1 20 19  
18  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
B1  
B2  
B3  
B4  
B5  
description  
17  
16  
15  
14  
These octal bus transceivers are designed for  
asynchronous communication between data  
buses. The devices transmit data from the A bus  
to the B bus or from the B bus to the A bus,  
depending on the logic level at the  
direction-control (DIR) input. The output-enable  
(OE) input can be used to disable the device so  
the buses are effectively isolated.  
9 10 11 12 13  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the device when it is powered down. The  
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN54ABTH245 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ABTH245 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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