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SN74ABTH16260DL PDF预览

SN74ABTH16260DL

更新时间： 2024-11-24 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
8页 126K
描述
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS

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中文翻译

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SN74ABTH16260DL 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SSOP
包装说明：0.300 INCH, PLASTIC, SSOP-56针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.42Is Samacsys：N
系列：ABTJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.41 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS EXCHANGER
最大I（ol）：0.064 A湿度敏感等级：1
位数：12功能数量：1
端口数量：3端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：63 mA传播延迟（tpd）：5.3 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Other Logic ICs最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.49 mm
Base Number Matches：1

SN74ABTH16260DL 数据手册

 浏览型号SN74ABTH16260DL的Datasheet PDF文件第2页浏览型号SN74ABTH16260DL的Datasheet PDF文件第3页浏览型号SN74ABTH16260DL的Datasheet PDF文件第4页浏览型号SN74ABTH16260DL的Datasheet PDF文件第5页浏览型号SN74ABTH16260DL的Datasheet PDF文件第6页浏览型号SN74ABTH16260DL的Datasheet PDF文件第7页 
SN54ABT16260, SN74ABTH16260  
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS204C – JUNE 1992 – REVISED MAY 1997  
SN54ABT16260 . . . WD PACKAGE  
SN74ABTH16260 . . . DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
OEA  
LE1B  
2B3  
GND  
2B2  
OE2B  
LEA2B  
2B4  
GND  
2B5  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2
3
4
5
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
2B1  
2B6  
6
V
V
7
CC  
CC  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
A1  
A2  
A3  
GND  
A4  
A5  
A6  
A7  
A8  
2B7  
2B8  
2B9  
8
at V  
= 5 V, T = 25°C  
CC  
A
9
High-Impedance State During Power Up  
and Power Down  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
High-Drive Outputs (–32-mA I , 64-mA I  
)
OH  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
OL  
A9  
GND  
A10  
A11  
A12  
1B8  
1B7  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Package and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Package Using 25-mil Center-to-Center  
Spacings  
V
V
CC  
CC  
1B1  
1B2  
GND  
1B3  
LE2B  
SEL  
1B6  
1B5  
GND  
1B4  
LEA1B  
OE1B  
description  
The SN54ABT16260 and SN74ABTH16260 are  
12-bit to 24-bit multiplexed D-type latches used in  
applications in which two separate data paths  
must be multiplexed onto, or demultiplexed from,  
a single data path. Typical applications include  
multiplexing and/or demultiplexing of address and  
data  
information  
in  
microprocessor  
or  
bus-interface applications. This device is also  
useful in memory-interleaving applications.  
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The  
output-enable (OE1B, OE2B, and OEA) inputs control the bus-transceiver functions. The OE1B and OE2B  
control signals also allow bank control in the A-to-B direction.  
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,  
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the  
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains  
latched until the latch-enable input is returned high.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

中文翻译

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SN74ABTH16260DL 替代型号

型号 品牌 替代类型 描述 数据表
74ABTH16260DLRG4 TI

完全替代

 ABT SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC, SSOP-56
SN74ABTH16260DLG4 TI

类似代替

 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABTH16260DLR TI

类似代替

 12-Bit To 24-Bit Multiplexed D-Type Latches With 3-State Outputs 56-SSOP -40 to 85

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SN74ABTH16260DLR TI

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 		4-to-1 Multiplexer/Demultiplexer Transceivers With 3-State Outputs 56-SSOP -40 to 85
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