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SN74ABTH16245DGV

更新时间： 2024-11-24 23:06:11
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德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
7页 103K
描述
16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN74ABTH16245DGV 数据手册

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SN54ABTH16245, SN74ABTH16245  
16-BIT BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS662I – MARCH 1996 – REVISED MARCH 1999  
SN54ABTH16245 . . . WD PACKAGE  
SN74ABTH16245 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
Typical V  
(Output Ground Bounce) < 1 V  
2
OLP  
at V  
= 5 V, T = 25°C  
3
CC  
A
4
High-Impedance State During Power Up  
and Power Down  
5
6
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
7
V
V
CC  
CC  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
Flow-Through Architecture Optimizes PCB  
Layout  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
V
V
CC  
CC  
2B5  
2B6  
GND  
2B7  
2B8  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
2DIR  
description  
The ’ABTH16245 devices are 16-bit noninverting  
3-state transceivers that provide synchronous  
two-way communication between data buses.  
The control-function implementation minimizes  
external timing requirements.  
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission  
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control  
(DIR) input. The output-enable (OE) input can be used to disable the devices so that the buses are effectively  
isolated.  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN54ABTH16245 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ABTH16245 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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