5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74ABT833NT
SN74ABT833NT PDF预览

SN74ABT833NT

更新时间： 2024-11-17 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
9页 156K
描述
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

阅读下载

中文翻译

获取价格

SN74ABT833NT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：7.8Is Samacsys：N
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ABT
JESD-30 代码：R-PDIP-T24JESD-609代码：e4
长度：31.64 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.064 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：38 mAProp。Delay @ Nom-Sup：5.3 ns
传播延迟（tpd）：5.3 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：7.62 mmBase Number Matches：1

SN74ABT833NT 数据手册

 浏览型号SN74ABT833NT的Datasheet PDF文件第2页浏览型号SN74ABT833NT的Datasheet PDF文件第3页浏览型号SN74ABT833NT的Datasheet PDF文件第4页浏览型号SN74ABT833NT的Datasheet PDF文件第5页浏览型号SN74ABT833NT的Datasheet PDF文件第6页浏览型号SN74ABT833NT的Datasheet PDF文件第7页 
SN54ABT833, SN74ABT833  
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS  
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997  
SN54ABT833 . . . JT PACKAGE  
SN74ABT833 . . . DW OR NT PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OEA  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
High-Drive Outputs (–32-mA I  
,
OH  
64-mA I  
)
OL  
Parity Error Flag With Parity  
Generator/Checker  
ERR 10  
CLR  
15 PARITY  
OEB  
CLK  
11  
12  
14  
13  
Register for Storage of the Parity Error Flag  
GND  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Plastic (NT) and  
Ceramic (JT) DIPs  
SN54ABT833 . . . FK PACKAGE  
(TOP VIEW)  
description  
4
3
2
1
28 27 26  
25  
The ’ABT833 8-bit to 9-bit parity transceivers are  
designedforcommunicationbetweendatabuses.  
When data is transmitted from the A bus to the  
B bus, a parity bit is generated. When data is  
transmitted from the B bus to the A bus with its  
corresponding parity bit, the open-collector  
parity-error (ERR) output indicates whether or not  
an error in the B data has occurred. The  
output-enable (OEA and OEB) inputs can be used  
to disable the device so that the buses are  
effectively isolated. The ’ABT833 provide true  
data at their outputs.  
5
A3  
A4  
A5  
NC  
A6  
A7  
A8  
B3  
B4  
B5  
NC  
B6  
B7  
B8  
6
24  
23  
22  
21  
20  
19  
7
8
9
10  
11  
12 13 14 15 16 17 18  
NC – No internal connection  
A 9-bit parity generator/checker generates a  
parity-odd (PARITY) output and monitors the  
parity of the I/O ports with the ERR flag. ERR is  
clocked into the register on the rising edge of the  
clock(CLK)input. Theerrorflagregisteriscleared  
with a low pulse on the clear (CLR) input. When  
both OEA and OEB are low, data is transferred  
from the A bus to the B bus and inverted parity is  
generated. Inverted parity is a forced error  
condition that gives the designer more system  
diagnostic capability.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

SN74ABT833NT 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT833DWE4 TI

完全替代

 ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, SOIC-24

与SN74ABT833NT相关器件

型号 品牌 获取价格 描述 数据表
SN74ABT834NT TI

获取价格

 		IC,BUS TRANSCEIVER,SINGLE,8-BIT,BICMOS-TTL,DIP,24PIN,PLASTIC
SN74ABT8373DW TI

获取价格

 		ABT SERIES, 8-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, PDSO24
SN74ABT8373DWR TI

获取价格

 		ABT SERIES, 8-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, PDSO24
SN74ABT8374DWR TI

获取价格

 		ABT SERIES, 8-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, PDSO24
SN74ABT841A TI

获取价格

 		10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT841ADB TI

获取价格

 		10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT841ADBLE TI

获取价格

 		10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS
SN74ABT841ADBR TI

获取价格

 		10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS
SN74ABT841ADBRE4 TI

获取价格

 		10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS
SN74ABT841ADBRG4 TI

获取价格

 		10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS

与SN74ABT833NT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证