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SN74ABT823DW PDF预览

SN74ABT823DW

更新时间： 2024-09-16 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
7页 112K
描述
9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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中文翻译

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SN74ABT823DW 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SO-24针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.26Is Samacsys：N
其他特性：WITH CLEAR AND CLOCK ENABLE控制类型：INDEPENDENT CONTROL
计数方向：UNIDIRECTIONAL系列：ABT
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：15.4 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：125000000 Hz
最大I（ol）：0.064 A湿度敏感等级：1
位数：9功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TUBE
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：38 mAProp。Delay @ Nom-Sup：6.8 ns
传播延迟（tpd）：6.8 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Bus Driver/Transceiver
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：7.5 mm
Base Number Matches：1

SN74ABT823DW 数据手册

 浏览型号SN74ABT823DW的Datasheet PDF文件第2页浏览型号SN74ABT823DW的Datasheet PDF文件第3页浏览型号SN74ABT823DW的Datasheet PDF文件第4页浏览型号SN74ABT823DW的Datasheet PDF文件第5页浏览型号SN74ABT823DW的Datasheet PDF文件第6页浏览型号SN74ABT823DW的Datasheet PDF文件第7页 
SN54ABT823, SN74ABT823  
9-BIT BUS-INTERFACE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS158E – JANUARY 1991 – REVISED MAY 1997  
SN54ABT823 . . . JT OR W PACKAGE  
SN74ABT823 . . . DB, DW, OR NT PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
1
2
3
4
5
6
7
8
9
24  
V
CC  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 CLKEN  
13 CLK  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
High-Impedance State During Power Up  
and Power Down  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
9D 10  
CLR 11  
GND 12  
Buffered Control Inputs to Reduce  
dc Loading Effects  
Package Options Include Plastic  
Small-Outline (DW) and Shrink  
Small-Outline (DB) Packages, Ceramic Chip  
Carriers (FK) and Flatpacks (W), and  
Standard Plastic (NT) and Ceramic (JT)  
DIPs  
SN54ABT823 . . . FK PACKAGE  
(TOP VIEW)  
4
3
2
1
28 27 26  
25  
5
3D  
4D  
5D  
NC  
6D  
7D  
8D  
3Q  
4Q  
5Q  
NC  
6Q  
7Q  
8Q  
description  
6
24  
23  
22  
21  
20  
19  
These 9-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing wider buffer  
registers, I/O ports, bidirectional bus drivers with  
parity, and working registers.  
7
8
9
10  
11  
12 13 14 15 16 17 18  
With the clock-enable (CLKEN) input low, the nine  
D-type edge-triggered flip-flops enter data on the  
low-to-high transitions of the clock. TakingCLKEN  
high disables the clock buffer, thus latching the  
outputs. Taking the clear (CLR) input low causes  
the nine Q outputs to go low, independently of the  
clock.  
NC – No internal connection  
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high  
or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without need for interface or pullup components.  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
The SN54ABT823 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ABT823 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

中文翻译

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SN74ABT823DW 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT823NT TI

完全替代

 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ABT823DWR TI

类似代替

 具有三态输出的 9 位总线接口触发器 | DW | 24 | -40 to 85
SN74ABT823DBR TI

类似代替

 9-Bit Bus-Interface Flip-Flops With 3-State Outputs 24-SSOP -40 to 85

与SN74ABT823DW相关器件

型号 品牌 获取价格 描述 数据表
SN74ABT823DWR TI

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 		具有三态输出的 9 位总线接口触发器 | DW | 24 | -40 to 85
SN74ABT823NSR TI

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 		暂无描述
SN74ABT823NSRE4 TI

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 		ABT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24
SN74ABT823NSRG4 TI

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 		ABT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24
SN74ABT823NT TI

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 		9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ABT823NTE4 TI

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 		ABT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDIP24, PLASTIC, DIP-24
SN74ABT8245 TI

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 		SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS
SN74ABT8245DB TI

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 		ABT SERIES, 8-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, PDSO24
SN74ABT8245DBR TI

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 		暂无描述
SN74ABT8245DW TI

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 		SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS

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