SN74ABT821A

更新时间： 2024-11-11 23:06:11

品牌	Logo	应用领域
德州仪器 - TI		触发器输出元件
页数	文件大小	规格书
7页	111K
描述
10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN74ABT821A 数据手册

SN54ABT821, SN74ABT821A

10-BIT BUS-INTERFACE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS193E – FEBRUARY 1991 – REVISED MAY 1997

SN54ABT821 . . . JT OR W PACKAGE

SN74ABT821A . . . DB, DW, OR NT PACKAGE

(TOP VIEW)

State-of-the-Art EPIC-ΙΙB BiCMOS Design

Significantly Reduces Power Dissipation

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

23 1Q

22 2Q

21 3Q

20 4Q

19 5Q

18 6Q

17 7Q

16 8Q

15 9Q

14 10Q

13 CLK

Typical V

(Output Ground Bounce) < 1 V

OLP

at V

= 5 V, T = 25°C

High-Impedance State During Power Up

and Power Down

High-Drive Outputs (–32-mA I , 64-mA I

)

Package Options Include Plastic

Small-Outline (DW) and Shrink

Small-Outline (DB) Packages, Ceramic Chip

Carriers (FK), Ceramic Flat (W) Package,

and Plastic (NT) and Ceramic (JT) DIPs

9D 10

10D 11

GND 12

SN54ABT821 . . . FK PACKAGE

(TOP VIEW)

description

These 10-bit flip-flops feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. They are

particularly suitable for implementing wider buffer

registers, I/O ports, bidirectional bus drivers with

parity, and working registers.

28 27 26

The ten flip-flops are edge-triggered D-type

flip-flops. On the positive transition of the clock

(CLK) input, the devices provide true data at the

Q outputs.

12 13 14 15 16 17 18

A buffered output-enable (OE) input can be used

to place the ten outputs in either a normal logic

state (high or low logic levels) or a high-impe-

dance state. In the high-impedance state, the

outputs neither load nor drive the bus lines

significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines without need for interface or pullup

components.

NC – No internal connection

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can

be entered while the outputs are in the high-impedance state.

When V

is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to V

the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup resistor;

The SN54ABT821 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ABT821A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

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与SN74ABT821A相关器件

型号	品牌	获取价格	描述	数据表
SN74ABT821ADB	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ABT821ADBLE	TI	获取价格	10-Bit Bus Interface Flip-Flops With 3-State Outputs 24-SSOP -40 to 85
SN74ABT821ADBRE4	TI	获取价格	ABT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24
SN74ABT821ADW	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ABT821ADWE4	TI	获取价格	ABT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24
SN74ABT821ADWR	TI	获取价格	具有三态输出的 10 位总线接口触发器 \| DW \| 24 \| -40 to 85
SN74ABT821ADWRE4	TI	获取价格	ABT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24
SN74ABT821ANSR	TI	获取价格	暂无描述
SN74ABT821ANSRE4	TI	获取价格	ABT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24
SN74ABT821ANSRG4	TI	获取价格	ABT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24

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