SN54ABT651, SN74ABT651
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS083E – JANUARY 1991 – REVISED APRIL 1998
SN54ABT651 . . . JT PACKAGE
SN74ABT651 . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
CLKAB
SAB
OEAB
A1
V
CC
1
24
23
22
21
20
19
18
17
16
15
14
CLKBA
SBA
OEBA
B1
2
Latch-Up Performance Exceeds 500 mA Per
JESD 17
3
4
A2
5
Typical V
(Output Ground Bounce) < 1 V
OLP
A3
B2
6
at V
= 5 V, T = 25°C
CC
A
A4
B3
7
High-Drive Outputs (–32-mA I
,
OH
A5
B4
8
64-mA I
)
OL
A6
B5
9
Multiplexed Real-Time and Stored Data
Inverting Data Paths
A7
B6
10
11
A8
B7
Package Options Include Plastic
13 B8
GND 12
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs
SN54ABT651 . . . FK PACKAGE
(TOP VIEW)
description
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. The
select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. A low input level selects real-time
data, and a high input level selects stored data.
4
3
2 1 28 27 26
5
6
7
8
9
25
OEBA
A1
A2
A3
NC
A4
A5
A6
24 B1
23 B2
22 NC
B3
B4
B5
21
20
19
10
11
12 13 14 15 16 17 18
Figure
1
illustrates the four fundamental
bus-management functions that can be
performed with the ’ABT651 devices.
NC – No internal connection
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all
the other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to V
through a
CC
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
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