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SN74ABT32543 PDF预览

SN74ABT32543

更新时间: 2024-09-23 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
9页 159K
描述
36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN74ABT32543 数据手册

 浏览型号SN74ABT32543的Datasheet PDF文件第2页浏览型号SN74ABT32543的Datasheet PDF文件第3页浏览型号SN74ABT32543的Datasheet PDF文件第4页浏览型号SN74ABT32543的Datasheet PDF文件第5页浏览型号SN74ABT32543的Datasheet PDF文件第6页浏览型号SN74ABT32543的Datasheet PDF文件第7页 
ꢇ ꢌ ꢍꢅꢎ ꢆꢊ ꢏꢐꢑ ꢎ ꢀꢆ ꢐꢏꢐꢒ ꢊꢅꢓꢀ ꢊꢆ ꢏꢄꢁ ꢀꢔ ꢐ ꢎꢕ ꢐ ꢏ  
ꢖ ꢎꢆ ꢗꢊ ꢇ ꢍꢀꢆꢄꢆ ꢐꢊ ꢘꢓ ꢆꢙ ꢓꢆ  
SCBS230B − JUNE 1992 − REVISED JULY 1994  
Members of the Texas Instruments  
Widebus+Family  
Distributed V  
and GND Pin Configuration  
CC  
Minimizes High-Speed Switching Noise  
High-Drive Outputs (32-mA I  
State-of-the-Art EPIC-ΙΙBBiCMOS Design  
,
OH  
Significantly Reduces Power Dissipation  
64-mA I  
)
OL  
Latch-Up Performance Exceeds 500 mA  
Bus-Hold Inputs Eliminate the Need for  
Per JEDEC Standard JESD-17  
External Pullup Resistors  
Typical V  
(Output Ground Bounce)  
Packaged in 100-Pin Plastic Thin Quad  
Flat (PZ) Package With 14 × 14-mm Body  
Using 0.5-mm Lead Pitch  
OLP  
< 0.8 V at V  
= 5 V, T = 25°C  
CC  
A
SN74ABT32543 . . . PZ PACKAGE  
(TOP VIEW)  
1009998 9796 959493 92 9190 89 8887 86 8584 83 8281 8079 7877 76  
1A9  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
75 1B9  
1A10  
GND  
1A11  
1A12  
1A13  
1A14  
GND  
1A15  
1A16  
1A17  
1A18  
74 1B10  
73 GND  
72 1B11  
71 1B12  
70 1B13  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
1B14  
GND  
1B15  
1B16  
1B17  
1B18  
V
V
CC  
CC  
2A1  
2A2  
2A3  
2A4  
GND  
2A5  
2A6  
2A7  
2A8  
GND  
2A9  
2A10  
2B1  
2B2  
2B3  
2B4  
GND  
2B5  
2B6  
2B7  
2B8  
GND  
2B9  
2B10  
26 272829 3031 32 33 343536 3738 3940 4142 43 4445 46 474849 50  
description  
The ABT32543 are 36-bit registered transceivers that contain two sets of D-type latches for temporary storage  
of data flowing in either direction. These devices can be used as two 18-bit transceivers or one 36-bit transceiver.  
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each  
register to permit independent control in either direction of data flow.  
Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1994, Texas Instruments Incorporated  
ꢓ ꢁꢛ ꢐꢀꢀ ꢘ ꢆꢗ ꢐꢏꢖ ꢎꢀ ꢐ ꢁ ꢘꢆꢐ ꢒ ꢜꢝ ꢞꢟ ꢠꢡꢢ ꢣꢤ ꢥꢦꢜ ꢢꢡ ꢦꢜꢧ ꢞꢦꢟ ꢙꢏ ꢘ ꢒ ꢓ ꢔꢆ ꢎꢘ ꢁ  
ꢪꢧ ꢩ ꢧ ꢤ ꢥ ꢜ ꢥ ꢩ ꢟ ꢭ  
5−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

SN74ABT32543 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABTH32543 TI

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