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SN74ABT32501PZR PDF预览

SN74ABT32501PZR

更新时间: 2024-09-23 19:55:15
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理输出元件逻辑集成电路
页数 文件大小 规格书
11页 190K
描述
ABT SERIES, DUAL 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PQFP100, PLASTIC, TQFP-100

SN74ABT32501PZR 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:unknown风险等级:5.63
其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION系列:ABT
JESD-30 代码:S-PQFP-G100长度:14 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
位数:18功能数量:2
端口数量:2端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
最大电源电流(ICC):90 mA传播延迟(tpd):5.4 ns
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

SN74ABT32501PZR 数据手册

 浏览型号SN74ABT32501PZR的Datasheet PDF文件第2页浏览型号SN74ABT32501PZR的Datasheet PDF文件第3页浏览型号SN74ABT32501PZR的Datasheet PDF文件第4页浏览型号SN74ABT32501PZR的Datasheet PDF文件第5页浏览型号SN74ABT32501PZR的Datasheet PDF文件第6页浏览型号SN74ABT32501PZR的Datasheet PDF文件第7页 
SN54ABTH32501, SN74ABTH32501  
36-BIT UNIVERSAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS229F – JUNE 1992 – REVISED MAY 1997  
Members of the Texas Instruments  
Widebus+ Family  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 5 V, T = 25°C  
CC  
A
High-Impedance State During Power Up  
and Power Down  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
CC  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Package Options Include 100-Pin Plastic  
Thin Quad Flat (PZ) Package With  
14 × 14-mm Body Using 0.5-mm Lead Pitch  
and Space-Saving 100-Pin Ceramic Quad  
Flat (HS) Package  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Released as DSCC SMD 5962-9557601NXD  
’ABTH32501 . . . PZ PACKAGE  
(TOP VIEW)  
1009998 9796 959493 929190898887868584 8382818079787776  
2B10  
2B9  
GND  
2B8  
2B7  
2B6  
2B5  
GND  
2B4  
2B3  
2B2  
2B1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
2A10  
2A9  
GND  
2A8  
2A7  
2A6  
2A5  
GND  
2A4  
2A3  
2A2  
2A1  
V
V
CC  
CC  
1B1  
1B2  
1B3  
1B4  
GND  
1B5  
1B6  
1B7  
1B8  
GND  
1B9  
1B10  
1A1  
1A2  
1A3  
1A4  
GND  
1A5  
1A6  
1A7  
1A8  
GND  
1A9  
1A10  
26272829303132333435363738394041424344454647484950  
The HS package is not production released.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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