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SN74ABT16833DLRG4 PDF预览

SN74ABT16833DLRG4

更新时间： 2024-11-14 05:29:39
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
13页 364K
描述
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

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中文翻译

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SN74ABT16833DLRG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.45
Is Samacsys：N其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ABTJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.41 mm
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：0.036 mA
Prop。Delay @ Nom-Sup：4.3 ns传播延迟（tpd）：4.3 ns
认证状态：Not Qualified施密特触发器：No
座面最大高度：2.79 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：7.49 mm
Base Number Matches：1

SN74ABT16833DLRG4 数据手册

 浏览型号SN74ABT16833DLRG4的Datasheet PDF文件第2页浏览型号SN74ABT16833DLRG4的Datasheet PDF文件第3页浏览型号SN74ABT16833DLRG4的Datasheet PDF文件第4页浏览型号SN74ABT16833DLRG4的Datasheet PDF文件第5页浏览型号SN74ABT16833DLRG4的Datasheet PDF文件第6页浏览型号SN74ABT16833DLRG4的Datasheet PDF文件第7页 
SN54ABT16833, SN74ABT16833  
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS  
SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997  
SN54ABT16833 . . . WD PACKAGE  
SN74ABT16833 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1OEB  
1CLK  
1ERR  
GND  
1A1  
1OEA  
1CLR  
1PARITY  
GND  
1B1  
1B2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
2
3
4
Typical V  
< 1 V at V  
(Output Ground Bounce)  
OLP  
CC  
5
= 5 V, T = 25°C  
A
1A2  
6
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
V
V
7
CC  
CC  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
8
Flow-Through Architecture Optimizes  
PCB Layout  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Parity-Error Flag With Parity  
Generator/Checker  
Register for Storage of Parity-Error Flag  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
V
V
CC  
CC  
The ’ABT16833 consist of two noninverting 8-bit  
to 9-bit parity bus transceivers and are designed  
for communication between data buses. For each  
transceiver, when data is transmitted from the  
A bus to the B bus, an odd-parity bit is generated  
and output on the parity I/O pin (1PARITY or  
2PARITY). When data is transmitted from the  
B bus to the A bus, 1PARITY (or 2PARITY) is  
configured as an input and combined with the  
B-input data to generate an active-low error flag if  
odd parity is not detected.  
2A7  
2A8  
GND  
2ERR  
2CLK  
2OEB  
2B7  
2B8  
GND  
2PARITY  
2CLR  
2OEA  
The error (1ERR or 2ERR) output is configured as an open-collector output. The B-to-A parity-error flag is  
clocked into 1ERR (or 2ERR) on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR (or 2ERR)  
is cleared (set high) by taking the clear (1CLR or 2CLR) input low.  
The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively  
isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity  
is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic  
capability.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

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SN74ABT16833DLRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT16833DLG4 TI

完全替代

 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN74ABT16833DL TI

完全替代

 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

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