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SN74ABT16646DGG PDF预览

SN74ABT16646DGG

更新时间： 2024-02-29 22:23:48
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
15页 245K
描述
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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中文翻译

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SN74ABT16646DGG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP-56针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.16Is Samacsys：N
其他特性：WITH DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIME DATA控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ABT
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：18.41 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：0.035 mA
Prop。Delay @ Nom-Sup：4.6 ns传播延迟（tpd）：4.9 ns
认证状态：Not Qualified施密特触发器：No
座面最大高度：2.79 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：7.49 mm
Base Number Matches：1

SN74ABT16646DGG 数据手册

 浏览型号SN74ABT16646DGG的Datasheet PDF文件第2页浏览型号SN74ABT16646DGG的Datasheet PDF文件第3页浏览型号SN74ABT16646DGG的Datasheet PDF文件第4页浏览型号SN74ABT16646DGG的Datasheet PDF文件第5页浏览型号SN74ABT16646DGG的Datasheet PDF文件第6页浏览型号SN74ABT16646DGG的Datasheet PDF文件第7页 
SN54ABT16646, SN74ABT16646  
16-BIT BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS212D – JUNE 1992 – REVISED JULY 1999  
SN54ABT16646 . . . WD PACKAGE  
SN74ABT16646 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1DIR  
1CLKAB  
1SAB  
GND  
1OE  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
2
1CLKBA  
1SBA  
GND  
1B1  
3
4
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
5
1A1  
1A2  
at V  
= 5 V, T = 25°C  
CC  
A
6
1B2  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
7
V
V
CC  
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Flow-Through Architecture Optimizes PCB  
Layout  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
The  
’ABT16646  
devices  
consist  
of  
bus-transceiver circuits, D-type flip-flops, and  
control circuitry arranged for multiplexed  
transmission of data directly from the input bus or  
from the internal registers.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2SBA  
2CLKBA  
2OE  
These devices can be used as two 8-bit  
transceivers or one 16-bit transceiver. Data on the  
A or B bus is clocked into the registers on the  
low-to-high transition of the appropriate clock  
(CLKAB or CLKBA) input. Figure 1 illustrates the  
four fundamental bus-management functions that  
can be performed with the ’ABT16646 devices.  
2SAB  
2CLKAB  
2DIR  
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the  
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The  
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry  
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition  
between stored and real-time data. The direction control (DIR) determines which bus receives data when OE  
is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the  
other register.  
When an output function is disabled, the input function is still enabled and can be used to store and transmit  
data. Only one of the two buses, A or B, can be driven at a time.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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