SN54ABT16640, SN74ABT16640
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS107C – APRIL 1992 – REVISED JANUARY 1997
SN54ABT16640 . . . WD PACKAGE
SN74ABT16640 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
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25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
2
3
Typical V
(Output Ground Bounce) < 1 V
4
OLP
at V
= 5 V, T = 25°C
5
CC
A
6
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
7
V
V
CC
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
Flow-Through Architecture Optimizes PCB
Layout
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
High-Drive Outputs (–32-mA I
,
OH
64-mA I
)
OL
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
V
V
CC
CC
description
2B5
2B6
GND
2B7
2B8
2A5
2A6
GND
2A7
2A8
2OE
The ’ABT16640 are inverting 16-bit transceivers
designed for asynchronous communication
between data buses.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. It allows
data transmission from the A bus to the B bus or
fromtheBbustotheAbus, dependingonthelogic
level at the direction-control (1DIR and 2DIR)
inputs. The output-enable (1OE and 2OE) inputs
can be used to disable the device so that the
buses are effectively isolated.
2DIR
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16640 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16640 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
DIR
L
OE
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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