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SN74ABT16623 PDF预览

SN74ABT16623

更新时间： 2024-11-27 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
7页 122K
描述
16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN74ABT16623 数据手册

 浏览型号SN74ABT16623的Datasheet PDF文件第2页浏览型号SN74ABT16623的Datasheet PDF文件第3页浏览型号SN74ABT16623的Datasheet PDF文件第4页浏览型号SN74ABT16623的Datasheet PDF文件第5页浏览型号SN74ABT16623的Datasheet PDF文件第6页浏览型号SN74ABT16623的Datasheet PDF文件第7页 
SN54ABT16623, SN74ABT16623  
16-BIT BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS211B – FEBRUARY 1991 – REVISED JANUARY 1997  
SN54ABT16623 . . . WD PACKAGE  
SN74ABT16623 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1OEAB  
1B1  
1B2  
GND  
1B3  
1OEBA  
1A1  
1A2  
GND  
1A3  
1A4  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
1B4  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
V
V
CC  
CC  
1B5  
1B6  
1A5  
1A6  
Flow-Through Architecture Optimizes PCB  
Layout  
GND 10  
1B7  
1B8  
39 GND  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
1A7  
1A8  
11  
12  
38  
37  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
2B1 13  
2B2 14  
GND 15  
2B3 16  
2B4 17  
36 2A1  
35 2A2  
34 GND  
33 2A3  
32 2A4  
description  
V
18  
31  
V
CC  
CC  
2B5 19  
30 2A5  
29 2A6  
28 GND  
27 2A7  
26 2A8  
25 2OEBA  
The ’ABT16623 are 16-bit transceivers designed  
for asynchronous communication between data  
buses. The control-function implementation  
allows for maximum flexibility in timing. The  
’ABT16623 provide true data at the outputs.  
2B6 20  
GND 21  
2B7 22  
2B8 23  
2OEAB 24  
These devices can be used as two 8-bit  
transceivers or one 16-bit transceiver. They allow  
data transmission from the A bus to the B bus or  
fromtheBbustotheAbus, dependingonthelogic  
levels at the output-enable (OEAB and OEBA)  
inputs. The output-enable inputs can be used to  
disable the device so that the buses are effectively  
isolated. The dual-enable configuration gives the  
transceivers the capability of storing data by  
simultaneously enabling OEAB and OEBA. Each  
output reinforces its input in this configuration.  
When both OEAB and OEBA are enabled and all  
other data sources to the two sets of bus lines are  
at high impedance, both sets of bus lines (32 total)  
remain at their last states.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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