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SN74ABT16601DLG4 PDF预览

SN74ABT16601DLG4

更新时间： 2024-11-26 15:52:03
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
15页 545K
描述
ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SSOP-56

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SN74ABT16601DLG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.52其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; WITH CLOCK ENABLE
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ABTJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.415 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：36 mA
Prop。Delay @ Nom-Sup：4.9 ns传播延迟（tpd）：4.7 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：7.49 mmBase Number Matches：1

SN74ABT16601DLG4 数据手册

 浏览型号SN74ABT16601DLG4的Datasheet PDF文件第2页浏览型号SN74ABT16601DLG4的Datasheet PDF文件第3页浏览型号SN74ABT16601DLG4的Datasheet PDF文件第4页浏览型号SN74ABT16601DLG4的Datasheet PDF文件第5页浏览型号SN74ABT16601DLG4的Datasheet PDF文件第6页浏览型号SN74ABT16601DLG4的Datasheet PDF文件第7页 
SN54ABT16601, SN74ABT16601  
18-BIT UNIVERSAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS210C – JUNE 1992 – REVISED JANUARY 1997  
SN54ABT16601 . . . WD PACKAGE  
SN74ABT16601 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
OEAB  
LEAB  
A1  
GND  
A2  
1
56 CLKENAB  
55 CLKAB  
54 B1  
UBT (Universal Bus Transceiver)  
2
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, Clocked, or Clock-Enabled Mode  
3
4
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GND  
B2  
B3  
5
6
A3  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
7
V
V
CC  
A4  
CC  
8
B4  
B5  
B6  
GND  
B7  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
9
A5  
A6  
GND  
A7  
A8  
A9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
= 5 V, T = 25°C  
CC  
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Flow-Through Architecture Optimizes PCB  
Layout  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
B8  
B9  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
description  
These 18-bit universal bus transceivers combine  
D-type latches and D-type flip-flops to allow data  
flow in transparent, latched, clocked, and  
clock-enabled modes.  
V
V
CC  
CC  
A16  
A17  
GND  
A18  
OEBA  
LEBA  
B16  
B17  
GND  
B18  
CLKBA  
CLKENBA  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA)inputs. The clock can be controlled by the  
clock-enable (CLKENAB and CLKENBA) inputs.  
For A-to-B data flow, the device operates in the  
transparent mode when LEAB is high. When  
LEAB is low, the A data is latched if CLKAB is held  
at a high or low logic level. If LEAB is low, the  
A data is stored in the latch/flip-flop on the  
low-to-high transition of CLKAB. Output enable  
OEAB is active low. When OEAB is low, the  
outputs are active. When OEAB is high, the  
outputs are in the high-impedance state.  
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54ABT16601 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ABT16601 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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SN74ABT16601DLG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT16601DLRG4 TI

完全替代

 18-Bit Universal Bus Transceivers With 3-State Outputs 56-SSOP -40 to 85
SN74ABT16601DLR TI

类似代替

 18-bit universal bus transceivers with 3-state outputs 56-SSOP -40 to 85
SN74ABT16601DL TI

类似代替

 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

与SN74ABT16601DLG4相关器件

型号 品牌 获取价格 描述 数据表
SN74ABT16601DLR TI

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 		18-bit universal bus transceivers with 3-state outputs 56-SSOP -40 to 85
SN74ABT16601DLRG4 TI

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 		18-Bit Universal Bus Transceivers With 3-State Outputs 56-SSOP -40 to 85
SN74ABT16623 TI

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 		16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT16623DGG TI

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 		16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT16623DGGR TI

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 		16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT16623DL TI

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 		16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT16623DLG4 TI

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 		16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT16623DLR TI

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 		16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT16623DLRG4 TI

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 		16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT16640 TI

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 		16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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