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SN74ABT16600DGG PDF预览

SN74ABT16600DGG

更新时间： 2024-11-25 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
7页 127K
描述
18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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中文翻译

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SN74ABT16600DGG 技术参数

生命周期：Obsolete包装说明：TSSOP,
Reach Compliance Code：unknown风险等级：5.67
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; WITH CLOCK ENABLE系列：ABT
JESD-30 代码：R-PDSO-G56长度：14 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
最大电源电流（ICC）：36 mA传播延迟（tpd）：5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：6.1 mm
Base Number Matches：1

SN74ABT16600DGG 数据手册

 浏览型号SN74ABT16600DGG的Datasheet PDF文件第2页浏览型号SN74ABT16600DGG的Datasheet PDF文件第3页浏览型号SN74ABT16600DGG的Datasheet PDF文件第4页浏览型号SN74ABT16600DGG的Datasheet PDF文件第5页浏览型号SN74ABT16600DGG的Datasheet PDF文件第6页浏览型号SN74ABT16600DGG的Datasheet PDF文件第7页 
SN54ABT16600, SN74ABT16600  
18-BIT UNIVERSAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS209B – JUNE 1992 – REVISED JANUARY 1997  
SN54ABT16600 . . . WD PACKAGE  
SN74ABT16600 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
OEAB  
LEAB  
A1  
GND  
A2  
1
56 CLKENAB  
55 CLKAB  
54 B1  
UBT (Universal Bus Transceiver)  
2
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, Clocked, or Clock-Enabled Mode  
3
4
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GND  
B2  
B3  
5
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015  
6
A3  
7
V
V
CC  
A4  
CC  
8
B4  
B5  
B6  
GND  
B7  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
9
A5  
A6  
GND  
A7  
A8  
A9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 5 V, T = 25°C  
CC  
A
Flow-Through Architecture Optimizes PCB  
Layout  
B8  
B9  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
description  
V
V
CC  
CC  
These 18-bit universal bus transceivers combine  
D-type latches and D-type flip-flops to allow data  
flow in transparent, latched, clocked, and  
clock-enabled modes.  
A16  
A17  
GND  
A18  
OEBA  
LEBA  
B16  
B17  
GND  
B18  
CLKBA  
CLKENBA  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA) inputs. The clock can be controlled by the  
clock-enable (CLKENAB and CLKENBA) inputs.  
For A-to-B data flow, the device operates in the  
transparent mode when LEAB is high. When  
LEAB is low, the A data is latched if CLKAB is held  
at a high or low logic level. If LEAB is low, the  
A-bus data is stored in the latch/flip-flop on the  
high-to-low transition of CLKAB. Output enable  
OEAB is active low. When OEAB is low, the  
outputs are active. When OEAB is high, the  
outputs are in the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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