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SN74ABT16501DLR PDF预览

SN74ABT16501DLR

更新时间： 2024-10-28 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
9页 150K
描述
18-bit universal bus transceivers with 3-state outputs 56-SSOP -40 to 85

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SN74ABT16501DLR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.16Is Samacsys：N
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ABT
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：18.41 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：76 mA
Prop。Delay @ Nom-Sup：4 ns传播延迟（tpd）：4.4 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Bus Driver/Transceiver最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：7.49 mmBase Number Matches：1

SN74ABT16501DLR 数据手册

 浏览型号SN74ABT16501DLR的Datasheet PDF文件第2页浏览型号SN74ABT16501DLR的Datasheet PDF文件第3页浏览型号SN74ABT16501DLR的Datasheet PDF文件第4页浏览型号SN74ABT16501DLR的Datasheet PDF文件第5页浏览型号SN74ABT16501DLR的Datasheet PDF文件第6页浏览型号SN74ABT16501DLR的Datasheet PDF文件第7页 
SN54ABT16501, SN74ABT16501  
18-BIT UNIVERSAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS086C – FEBRUARY 1991 – REVISED JANUARY 1997  
SN54ABT16501 . . . WD PACKAGE  
SN74ABT16501 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
OEAB  
LEAB  
A1  
GND  
A2  
GND  
CLKAB  
B1  
GND  
B2  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
A3  
B3  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
V
V
CC  
CC  
A4  
A5  
B4  
B5  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
A6 10  
47 B6  
GND  
A7  
GND  
B7  
11  
12  
46  
45  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 5 V, T = 25°C  
CC  
A
A8 13  
A9 14  
44 B8  
Flow-Through Architecture Optimizes PCB  
Layout  
43 B9  
A10 15  
A11 16  
A12 17  
GND 18  
A13 19  
A14 20  
A15 21  
42 B10  
41 B11  
40 B12  
39 GND  
38 B13  
37 B14  
36 B15  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
V
22  
35  
V
CC  
CC  
A16 23  
34 B16  
These 18-bit universal bus transceivers consist of  
storage elements that can operate either as  
D-type latches or D-type flip-flops to allow data  
flow in transparent or clocked modes.  
A17 24  
33 B17  
GND 25  
A18 26  
32 GND  
31 B18  
OEBA 27  
LEBA 28  
30 CLKBA  
29 GND  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA) inputs. For A-to-B data flow, the device  
operates in the transparent mode when LEAB is  
high. When LEAB is low, the A data is latched if  
CLKAB is held at a high or low logic level. If LEAB  
is low, the A data is stored in the latch/flip-flop on  
the low-to-high transition of CLKAB. When OEAB  
is high, the outputs are active. When OEAB is low,  
the outputs are in the high-impedance state.  
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are  
complementary (OEAB is active high and OEBA is active low).  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor and OE should be tied to V  
determined by the current-sourcing/current-sinking capability of the driver.  
through a pullup resistor; the minimum value of the resistor is  
CC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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SN74ABT16501DLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT16501DLRG4 TI

完全替代

 18-Bit Universal Bus Transceivers With 3-State Outputs 56-SSOP -40 to 85
SN74ABT16501DL TI

完全替代

 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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