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SN74ABT16500B PDF预览

SN74ABT16500B

更新时间： 2024-11-25 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
9页 151K
描述
18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN74ABT16500B 数据手册

 浏览型号SN74ABT16500B的Datasheet PDF文件第2页浏览型号SN74ABT16500B的Datasheet PDF文件第3页浏览型号SN74ABT16500B的Datasheet PDF文件第4页浏览型号SN74ABT16500B的Datasheet PDF文件第5页浏览型号SN74ABT16500B的Datasheet PDF文件第6页浏览型号SN74ABT16500B的Datasheet PDF文件第7页 
SN54ABT16500B, SN74ABT16500B  
18-BIT UNIVERSAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS057G – DECEMBER 1990 – REVISED MAY 1997  
SN54ABT16500B . . . WD PACKAGE  
SN74ABT16500B . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
OEAB  
LEAB  
A1  
GND  
A2  
GND  
CLKAB  
B1  
GND  
B2  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
A3  
B3  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015  
V
V
CC  
CC  
A4  
A5  
B4  
B5  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
A6 10  
47 B6  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
GND  
A7  
GND  
B7  
11  
12  
46  
45  
= 5 V, T = 25°C  
CC  
A
High-Impedance State During Power Up  
and Power Down  
A8 13  
A9 14  
44 B8  
43 B9  
Flow-Through Architecture Optimizes PCB  
Layout  
A10 15  
A11 16  
A12 17  
GND 18  
A13 19  
A14 20  
A15 21  
42 B10  
41 B11  
40 B12  
39 GND  
38 B13  
37 B14  
36 B15  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
V
22  
35  
V
CC  
CC  
description  
A16 23  
A17 24  
34 B16  
33 B17  
These 18-bit universal bus transceivers combine  
D-type latches and D-type flip-flops to allow data  
flow in transparent, latched, and clocked modes.  
GND 25  
A18 26  
32 GND  
31 B18  
OEBA 27  
LEBA 28  
30 CLKBA  
29 GND  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA) inputs. For A-to-B data flow, the device  
operates in the transparent mode when LEAB is  
high. When LEAB is low, the A data is latched if  
CLKAB is held at a high or low logic level. If LEAB  
is low, the A data is stored in the latch/flip-flop on  
the high-to-low transition of CLKAB. OEAB is  
active-high. When OEAB is high, the outputs are  
active. When OEAB is low, the outputs are in the  
high-impedance state.  
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are  
complementary (OEAB is active high and OEBA is active low).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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