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SN74ABT16373ADLR PDF预览

SN74ABT16373ADLR

更新时间： 2024-11-25 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
11页 195K
描述
16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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中文翻译

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SN74ABT16373ADLR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP, SSOP48,.4针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.01
其他特性：TYP VOLP < 0.8V @ VCC = 5V, TA = 25 DEG C控制类型：ENABLE LOW/HIGH
计数方向：UNIDIRECTIONAL系列：ABT
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：15.88 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP48,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：85 mA
Prop。Delay @ Nom-Sup：6.3 ns传播延迟（tpd）：6.1 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Bus Driver/Transceiver最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.49 mm
Base Number Matches：1

SN74ABT16373ADLR 数据手册

 浏览型号SN74ABT16373ADLR的Datasheet PDF文件第2页浏览型号SN74ABT16373ADLR的Datasheet PDF文件第3页浏览型号SN74ABT16373ADLR的Datasheet PDF文件第4页浏览型号SN74ABT16373ADLR的Datasheet PDF文件第5页浏览型号SN74ABT16373ADLR的Datasheet PDF文件第6页浏览型号SN74ABT16373ADLR的Datasheet PDF文件第7页 
SN54ABT16373A, SN74ABT16373A  
16-BIT TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS160C – DECEMBER 1992 – REVISED MAY 1997  
SN54ABT16373A . . . WD PACKAGE  
SN74ABT16373A . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
2
3
4
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
5
= 5 V, T = 25°C  
CC  
A
6
High-Impedance State During Power Up  
and Power Down  
V
V
7
CC  
CC  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
8
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Flow-Through Architecture Optimizes PCB  
Layout  
High-Drive Outputs (–32-mA I , 64-mA I  
)
OL  
OH  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
V
V
CC  
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
description  
The ’ABT16373A are 16-bit transparent D-type  
latches with 3-state outputs designed specifically  
for driving highly capacitive or relatively  
low-impedance loads. They are particularly  
suitable for implementing buffer registers, I/O  
ports, bidirectional bus drivers, and working  
registers.  
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,  
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up  
at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
The SN54ABT16373A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ABT16373A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

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SN74ABT16373ADLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT16373ADLG4 TI

完全替代

 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT16373ADLRG4 TI

完全替代

 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT16373ADL TI

类似代替

 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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