SN54ABT162601, SN74ABT162601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS247G – AUGUST 1992 – REVISED JULY 1998
SN54ABT162601 . . . WD PACKAGE
SN74ABT162601 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
B-Port Outputs Have Equivalent 25-Ω
Series Resistors, So No External Resistors
Are Required
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56
55
54
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51
50
49
48
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46
45
44
43
42
41
40
39
38
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OEAB
LEAB
A1
CLKENAB
CLKAB
B1
2
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
3
4
GND
A2
GND
B2
5
UBT (Universal Bus Transceiver)
6
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
A3
B3
7
V
V
B4
CC
A4
CC
8
9
A5
A6
B5
B6
Latch-Up Performance Exceeds 500 mA Per
JESD 17
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
A7
A8
GND
B7
B8
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 5 V, T = 25°C
CC
A
High-Impedance State During Power Up
and Power Down
A9
B9
A10
A11
A12
GND
A13
A14
A15
B10
B11
B12
GND
B13
B14
B15
Flow-Through Architecture Optimizes PCB
Layout
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
V
V
CC
CC
A16
A17
GND
A18
OEBA
LEBA
B16
B17
GND
B18
CLKBA
CLKENBA
description
These 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA)inputs. The clock can be controlled by the
clock-enable (CLKENAB and CLKENBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the
A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLKAB. Output-enable OEAB is active-low. When OEAB is low,
the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A
is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA.
The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors
to reduce overshoot and undershoot.
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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