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SN74ABT162601DGGR PDF预览

SN74ABT162601DGGR

更新时间： 2024-10-02 02:58:15
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 127K
描述
18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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中文翻译

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SN74ABT162601DGGR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP56,.3,20针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.63其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; WITH CLOCK ENABLE
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ABTJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：14 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.064 A湿度敏感等级：1
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：36 mAProp。Delay @ Nom-Sup：5.7 ns
传播延迟（tpd）：5.5 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：6.1 mm

SN74ABT162601DGGR 数据手册

 浏览型号SN74ABT162601DGGR的Datasheet PDF文件第2页浏览型号SN74ABT162601DGGR的Datasheet PDF文件第3页浏览型号SN74ABT162601DGGR的Datasheet PDF文件第4页浏览型号SN74ABT162601DGGR的Datasheet PDF文件第5页浏览型号SN74ABT162601DGGR的Datasheet PDF文件第6页浏览型号SN74ABT162601DGGR的Datasheet PDF文件第7页 
SN54ABT162601, SN74ABT162601  
18-BIT UNIVERSAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS247G – AUGUST 1992 – REVISED JULY 1998  
SN54ABT162601 . . . WD PACKAGE  
SN74ABT162601 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
B-Port Outputs Have Equivalent 25-Ω  
Series Resistors, So No External Resistors  
Are Required  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEAB  
LEAB  
A1  
CLKENAB  
CLKAB  
B1  
2
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
3
4
GND  
A2  
GND  
B2  
5
UBT (Universal Bus Transceiver)  
6
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, Clocked, or Clock-Enabled Mode  
A3  
B3  
7
V
V
B4  
CC  
A4  
CC  
8
9
A5  
A6  
B5  
B6  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
A7  
A8  
GND  
B7  
B8  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 5 V, T = 25°C  
CC  
A
High-Impedance State During Power Up  
and Power Down  
A9  
B9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
Flow-Through Architecture Optimizes PCB  
Layout  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
V
V
CC  
CC  
A16  
A17  
GND  
A18  
OEBA  
LEBA  
B16  
B17  
GND  
B18  
CLKBA  
CLKENBA  
description  
These 18-bit universal bus transceivers combine  
D-type latches and D-type flip-flops to allow data  
flow in transparent, latched, and clocked modes.  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA)inputs. The clock can be controlled by the  
clock-enable (CLKENAB and CLKENBA) inputs.  
For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the  
A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the  
latch/flip-flop on the low-to-high transition of CLKAB. Output-enable OEAB is active-low. When OEAB is low,  
the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A  
is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA.  
The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors  
to reduce overshoot and undershoot.  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

中文翻译

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SN74ABT162601DGGR 替代型号

型号 品牌 替代类型 描述 数据表
74ABT162601DGGRG4 TI

完全替代

 ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
74ABT162601DGGRE4 TI

类似代替

 ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
SN74ABT162601DGG TI

类似代替

 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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