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SN74ABT162244 PDF预览

SN74ABT162244

更新时间： 2024-11-20 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
12页 214K
描述
16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN74ABT162244 数据手册

 浏览型号SN74ABT162244的Datasheet PDF文件第2页浏览型号SN74ABT162244的Datasheet PDF文件第3页浏览型号SN74ABT162244的Datasheet PDF文件第4页浏览型号SN74ABT162244的Datasheet PDF文件第5页浏览型号SN74ABT162244的Datasheet PDF文件第6页浏览型号SN74ABT162244的Datasheet PDF文件第7页 
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ꢇ ꢈ ꢌꢅꢍ ꢆ ꢅꢎꢏ ꢏ ꢐꢑꢀꢒ ꢓ ꢑꢍ ꢔ ꢐꢑ  
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ꢕ ꢍꢆ ꢖ ꢗ ꢌꢀꢆꢄꢆ ꢐ ꢘ ꢎꢆ ꢙꢎ ꢆ  
SCBS238E − JUNE 1992 − REVISED JUNE 2004  
SN54ABT162244 . . . WD PACKAGE  
SN74ABT162244 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
D
D
Members of the Texas Instruments  
Widebus E Family  
Output Ports Have Equivalent 25-Ω Series  
Resistors, So No External Resistors Are  
Required  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
2OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
D
D
D
D
D
D
Typical V  
(Output Ground Bounce)  
OLP  
3
<1 V at V  
= 5 V, T = 25°C  
4
CC  
A
5
High-Impedance State During Power Up  
and Power Down  
6
7
V
V
I
and Power-Up 3-State Support Hot  
CC  
CC  
off  
8
2Y1  
2Y2  
GND  
2Y3  
2Y4  
3Y1  
3Y2  
GND  
3Y3  
3Y4  
2A1  
2A2  
GND  
2A3  
2A4  
3A1  
3A2  
GND  
3A3  
3A4  
Insertion  
9
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 500 mA Per  
JESD-17  
description/ordering information  
V
V
CC  
CC  
The ’ABT162244 devices are 16-bit buffers and  
line drivers designed specifically to improve both  
the performance and density of 3-state memory  
address drivers, clock drivers, and bus-oriented  
receivers and transmitters. These devices can be  
used as four 4-bit buffers, two 8-bit buffers, or one  
16-bit buffer. These devices provide noninverting  
4Y1  
4Y2  
GND  
4Y3  
4Y4  
4A1  
4A2  
GND  
4A3  
4A4  
3OE  
4OE  
outputs  
and  
symmetrical  
active-low  
output-enable (OE) inputs.  
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to  
reduce overshoot and undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74ABT162244DL  
SSOP − DL  
ABT162244  
Tape and reel  
SN74ABT162244DLR  
SN74ABT162244DGGR  
SN74ABT162244DGVR  
SNJ54ABT162244WD  
−40°C to 85°C  
−55°C to 125°C  
TSSOP − DGG Tape and reel  
ABT162244  
TVSOP − DGV  
CFP − WD  
Tape and reel  
Tube  
AH2244  
SNJ54ABT162244WD  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
ꢙꢑ ꢘ ꢓꢎ ꢚ ꢆꢍ ꢘ ꢁ ꢓ ꢄꢆꢄ ꢛꢜ ꢝ ꢞꢟ ꢠ ꢡꢢ ꢛꢞꢜ ꢛꢣ ꢤꢥ ꢟ ꢟ ꢦꢜꢢ ꢡꢣ ꢞꢝ ꢧꢥꢨ ꢩꢛꢤ ꢡꢢ ꢛꢞꢜ ꢪꢡ ꢢꢦ ꢫ  
ꢙꢟ ꢞ ꢪꢥꢤ ꢢ ꢣ ꢤ ꢞꢜ ꢝꢞ ꢟ ꢠ ꢢ ꢞ ꢣ ꢧꢦ ꢤ ꢛꢝ ꢛꢤꢡ ꢢꢛ ꢞꢜꢣ ꢧꢦ ꢟ ꢢꢬ ꢦ ꢢꢦ ꢟ ꢠꢣ ꢞꢝ ꢆꢦꢭ ꢡꢣ ꢍꢜꢣ ꢢꢟ ꢥꢠ ꢦꢜꢢ ꢣ  
ꢣ ꢢ ꢡ ꢜꢪ ꢡ ꢟꢪ ꢮ ꢡ ꢟꢟ ꢡ ꢜ ꢢꢯꢫ ꢙꢟ ꢞ ꢪꢥꢤ ꢢꢛꢞꢜ ꢧꢟ ꢞꢤ ꢦꢣ ꢣꢛ ꢜꢰ ꢪꢞꢦ ꢣ ꢜꢞꢢ ꢜꢦ ꢤꢦ ꢣꢣ ꢡꢟ ꢛꢩ ꢯ ꢛꢜꢤ ꢩꢥꢪ ꢦ  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
Copyright 2004, Texas Instruments Incorporated  
ꢘ ꢜ ꢧ ꢟ ꢞꢪ ꢥꢤ ꢢꢣ ꢤꢞ ꢠꢧ ꢩꢛ ꢡꢜ ꢢ ꢢꢞ ꢱꢍ ꢲꢌ ꢙꢑ ꢏ ꢌꢗꢳꢂ ꢗꢂꢊ ꢡꢩꢩ ꢧꢡ ꢟ ꢡ ꢠꢦ ꢢꢦꢟ ꢣ ꢡ ꢟ ꢦ ꢢꢦ ꢣꢢꢦ ꢪ  
ꢥ ꢜꢩ ꢦꢣꢣ ꢞ ꢢꢬꢦ ꢟ ꢮꢛ ꢣꢦ ꢜ ꢞꢢꢦ ꢪꢫ ꢘ ꢜ ꢡꢩ ꢩ ꢞ ꢢꢬꢦ ꢟ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢣ ꢊ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢛꢞ ꢜ  
ꢧ ꢟ ꢞꢤꢦ ꢣꢣꢛ ꢜꢰ ꢪ ꢞꢦꢣ ꢜ ꢞꢢ ꢜ ꢦꢤꢦꢣ ꢣꢡꢟ ꢛ ꢩꢯ ꢛ ꢜꢤꢩ ꢥ ꢪꢦ ꢢꢦꢣ ꢢꢛꢜ ꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠꢦ ꢢꢦꢟ ꢣ ꢫ  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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SN74ABT162244 替代型号

型号 品牌 替代类型 描述 数据表
SN54ABT162244 TI

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