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SN74ABT125PWR PDF预览

SN74ABT125PWR

更新时间： 2024-11-24 22:53:35
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德州仪器 - TI 输出元件
页数 文件大小 规格书
18页 637K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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SN74ABT125PWR 数据手册

 浏览型号SN74ABT125PWR的Datasheet PDF文件第2页浏览型号SN74ABT125PWR的Datasheet PDF文件第3页浏览型号SN74ABT125PWR的Datasheet PDF文件第4页浏览型号SN74ABT125PWR的Datasheet PDF文件第5页浏览型号SN74ABT125PWR的Datasheet PDF文件第6页浏览型号SN74ABT125PWR的Datasheet PDF文件第7页 
SN54ABT125, SN74ABT125  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002  
Typical V  
(Output Ground Bounce)  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
OLP  
<1 V at V  
= 5 V, T = 25°C  
CC  
A
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
High-Drive Outputs (–32-mA I , 64-mA I  
)
OH  
OL  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
SN54ABT125 . . . J OR W PACKAGE  
SN74ABT125 . . . D, DB, N, NS,  
OR PW PACKAGE  
SN74ABT125 . . . RGY PACKAGE  
(TOP VIEW)  
SN54ABT125 . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1
14  
3
2
1
20 19  
18 4A  
1Y  
NC  
4
5
6
7
8
13  
12  
11  
10  
9
2
3
4
5
6
1A  
1Y  
2OE  
2A  
4OE  
4A  
4Y  
3OE  
3A  
17  
16  
15  
14  
NC  
4Y  
4A  
4Y  
3OE  
3A  
3Y  
2OE  
NC  
NC  
3OE  
2A  
2Y  
9 10 11 12 13  
7
8
GND  
8
NC – No internal connection  
description/ordering information  
The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is  
disabled when the associated output-enable (OE) input is high.  
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74ABT125N  
SN74ABT125N  
QFN – RGY  
Tape and reel  
Tube  
SN74ABT125RGYR AB125  
SN74ABT125D  
ABT125  
SOIC – D  
–40°C to 85°C  
–55°C to 125°C  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74ABT125DR  
SOP – NS  
SSOP – DB  
TSSOP – PW  
CDIP – J  
SN74ABT125NSR  
SN74ABT125DBR  
SN74ABT125PWR  
SNJ54ABT125J  
ABT125  
AB125  
AB125  
SNJ54ABT125J  
SNJ54ABT125W  
SNJ54ABT125FK  
CFP – W  
Tube  
SNJ54ABT125W  
SNJ54ABT125FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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SN74ABT125PWR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT125PWE4 TI

完全替代

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74ABT125PWLE TI

完全替代

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74ABT125PW TI

完全替代

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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