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SN65LVDS96DGGR PDF预览

SN65LVDS96DGGR

更新时间： 2024-11-25 12:33:11
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德州仪器 - TI /
页数 文件大小 规格书
17页 340K
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LVDS SERDES RECEIVER

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SN65LVDS96DGGR 数据手册

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SN65LVDS96  
www.ti.com  
SLLS296H–MAY 1998–REVISED JULY 2006  
LVDS SERDES RECEIVER  
FEATURES  
DGG PACKAGE  
(TOP VIEW)  
•
•
•
3:21 Data Channel Compression at up to  
1.428 Gigabits/s Throughput  
D17  
D18  
GND  
D19  
V
CC  
1
48  
47  
46  
45  
44  
43  
42  
Suited for Point-to-Point Subsystem  
Communication With Very Low EMI  
D16  
D15  
D14  
GND  
D13  
2
3
3 Data Channels and Clock Low-Voltage  
Differential Channels in and 21 Data and  
Clock Low-Voltage TTL Channels Out  
4
D20  
5
NC  
6
•
Operates From a Single 3.3-V Supply and 250  
mW (Typ)  
LVDSGND  
A0M  
7
V
CC  
8
41 D12  
•
•
•
•
5-V Tolerant SHTDN Input  
9
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
A0P  
A1M  
D11  
D10  
GND  
D9  
Rising Clock Edge Triggered Outputs  
Bus Pins Tolerate 4-kV HBM ESD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
A1P  
LVDSV  
CC  
Packaged in Thin Shrink Small-Outline  
Package With 20 Mil Terminal Pitch  
LVDSGND  
A2M  
V
CC  
D8  
D7  
•
•
Consumes <1 mW When Disabled  
A2P  
Wide Phase-Lock Input Frequency Range  
20 MHz to 68 MHz  
CLKINM  
CLKINP  
LVDSGND  
PLLGND  
D6  
GND  
D5  
•
•
No External Components Required for PLL  
Inputs Meet or Exceed the Requirements of  
ANSI EIA/TIA-644 Standard  
D4  
PLLV  
D3  
V
CC  
PLLGND  
SHTDN  
CLKOUT  
D0  
•
•
Industrial Temperature Qualified  
TA = –40°C to 85°C  
CC  
D2  
D1  
GND  
Replacement for the DS90CR216  
DESCRIPTION  
The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift  
registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single  
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such asthe  
SN65LVDS95, over four balanced-pair conductors and expansion to 21 bits of single-ended LVTTL synchronous  
data at a lower transfer rate.  
When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times the  
LVDS input clock (CLKIN). The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A  
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the  
expanded data. The SN65LVDS96 presents valid data on the rising edge of the output clock (CLKOUT).  
The SN65LVDS96 requires only four line termination resistors for the differential inputs and little or no control.  
The data bus appears the same at the input to the transmitter and output of the receiver with data transmission  
transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN)  
active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on  
this signal clears all internal registers to a low level.  
The SN65LVDS96 is characterized for operation over ambient air temperatures of –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1998–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN65LVDS96DGGR 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS96DGGG4 TI

完全替代

 Serdes（串行器/解串器）接收器 | DGG | 48
SN65LVDS96DGG TI

完全替代

 LVDS SERDES RECEIVER

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