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SN65LVDS96DGG PDF预览

SN65LVDS96DGG

更新时间： 2024-11-24 22:25:31
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
14页 190K
描述
LVDS SERDES RECEIVER

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SN65LVDS96DGG 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.73Is Samacsys：N
差分输出：NO输入特性：DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：LINE RECEIVER接口标准：EIA-644; TIA-644
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：12.5 mm湿度敏感等级：2
功能数量：3端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：TOTEM-POLE最大输出低电流：0.00002 A
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：
接收器位数：3座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：82 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

SN65LVDS96DGG 数据手册

 浏览型号SN65LVDS96DGG的Datasheet PDF文件第2页浏览型号SN65LVDS96DGG的Datasheet PDF文件第3页浏览型号SN65LVDS96DGG的Datasheet PDF文件第4页浏览型号SN65LVDS96DGG的Datasheet PDF文件第5页浏览型号SN65LVDS96DGG的Datasheet PDF文件第6页浏览型号SN65LVDS96DGG的Datasheet PDF文件第7页 
SN65LVDS96  
LVDS SERDES RECEIVER  
SLLS296F – MAY 1998 – REVISED FEBRUARY 2000  
DGG PACKAGE  
(TOP VIEW)  
3:21 Data Channel Expansion at up to  
1.3 Gigabits per Second Throughput  
Suited for Point-to-Point Subsystem  
Communication With Very Low EMI  
D17  
D18  
V
CC  
1
48  
47  
46  
45  
44  
43  
42  
D16  
D15  
D14  
GND  
D13  
2
3 Data Channels and Clock Low-Voltage  
Differential Channels in and 21 Data and  
Clock Low-Voltage TTL Channels Out  
GND  
D19  
3
4
D20  
5
NC  
6
Operates From a Single 3.3-V Supply and  
250 mW (Typ)  
LVDSGND  
A0M  
7
V
CC  
8
41 D12  
40 D11  
5-V Tolerant SHTDN Input  
A0P  
9
Rising Clock Edge Triggered Outputs  
Bus Pins Tolerate 4-kV HBM ESD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
A1M  
D10  
GND  
D9  
A1P  
Packaged in Thin Shrink Small-Outline  
Package With 20 Mil Terminal Pitch  
LVDSV  
CC  
LVDSGND  
A2M  
V
CC  
Consumes <1 mW When Disabled  
D8  
A2P  
D7  
Wide Phase-Lock Input Frequency Range  
20 MHz to 67 MHz  
CLKINM  
CLKINP  
LVDSGND  
PLLGND  
D6  
GND  
D5  
No External Components Required for PLL  
Inputs Meet or Exceed the Requirements of  
ANSI EIA/TIA-644 Standard  
D4  
PLLV  
D3  
CC  
Industrial Temperature Qualified  
PLLGND  
SHTDN  
CLKOUT  
D0  
V
CC  
T = –40°C to 85°C  
A
D2  
Replacement for the DS90CR216  
D1  
GND  
description  
The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift  
registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single  
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as  
the SN65LVDS95, over four balanced-pair conductors and expansion to 21 bits of single-ended LVTTL  
synchronous data at a lower transfer rate.  
When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times the  
LVDS input clock (CLKIN). The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A  
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for  
the expanded data. The SN65LVDS96 presents valid data on the rising edge of the output clock (CLKOUT).  
The SN65LVDS96 requires only four line termination resistors for the differential inputs and little or no control.  
The data bus appears the same at the input to the transmitter and output of the receiver with data transmission  
transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN)  
active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level  
on this signal clears all internal registers to a low level.  
The SN65LVDS96 is characterized for operation over ambient air temperatures of –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

中文翻译

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SN65LVDS96DGG 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS96DGGG4 TI

完全替代

 Serdes（串行器/解串器）接收器 | DGG | 48
SN65LVDS96DGGR TI

完全替代

 LVDS SERDES RECEIVER

与SN65LVDS96DGG相关器件

型号 品牌 获取价格 描述 数据表
SN65LVDS96DGGG4 TI

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 		Serdes（串行器/解串器）接收器 | DGG | 48
SN65LVDS96DGGR TI

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 		LVDS SERDES RECEIVER
SN65LVDS96IDGGR TI

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 		5 LINE TRANSCEIVER, PDSO48
SN65LVDT100 TI

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 		DIFFERENTIAL TRANSLATOR/REPEATER
SN65LVDT100D TI

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 		DIFFERENTIAL TRANSLATOR/REPEATER
SN65LVDT100DG4 TI

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 		DIFFERENTIAL TRANSLATOR/REPEATER
SN65LVDT100DGK TI

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 		DIFFERENTIAL TRANSLATOR/REPEATER
SN65LVDT100DGKG4 TI

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 		DIFFERENTIAL TRANSLATOR/REPEATER
SN65LVDT100DGKR TI

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 		DIFFERENTIAL TRANSLATOR/REPEATER
SN65LVDT100DGKRG4 TI

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 		DIFFERENTIAL TRANSLATOR/REPEATER

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