5秒后页面跳转
捷配首页

Datasheet > 驱动程序和接口 > 线路驱动器或接收器> SN65LVDS94DGG
SN65LVDS94DGG PDF预览

SN65LVDS94DGG

更新时间： 2024-02-25 17:35:00
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管PC
页数 文件大小 规格书
14页 192K
描述
LVDS SERDES RECEIVER

阅读下载

中文翻译

获取价格

SN65LVDS94DGG 技术参数

生命周期：Obsolete包装说明：TSSOP,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.7
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：GENERAL PURPOSEJESD-30 代码：R-PDSO-G56
长度：14 mm功能数量：5
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态：Not Qualified
接收器位数：1座面最大高度：1.2 mm
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

SN65LVDS94DGG 数据手册

 浏览型号SN65LVDS94DGG的Datasheet PDF文件第2页浏览型号SN65LVDS94DGG的Datasheet PDF文件第3页浏览型号SN65LVDS94DGG的Datasheet PDF文件第4页浏览型号SN65LVDS94DGG的Datasheet PDF文件第5页浏览型号SN65LVDS94DGG的Datasheet PDF文件第6页浏览型号SN65LVDS94DGG的Datasheet PDF文件第7页 
SN65LVDS94  
LVDS SERDES RECEIVER  
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000  
DGG PACKAGE  
(TOP VIEW)  
4:28 Data Channel Expansion at up to  
1.820 Gigabits per Second Throughput  
Suited for Point-to-Point Subsystem  
Communication With Very Low EMI  
D22  
D23  
V
CC  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
D21  
D20  
D19  
GND  
D18  
D17  
D16  
2
4 Data Channels and Clock Low-Voltage  
Differential Channels in and 28 Data and  
Clock Out Low-Voltage TTL Channels Out  
D24  
3
GND  
4
D25  
5
Operates From a Single 3.3-V Supply and  
250 mW (Typ)  
D26  
6
D27  
7
LVDSGND  
A0M  
5-V Tolerant SHTDN Input  
8
V
9
CC  
Rising Clock Edge Triggered Outputs  
Bus Pins Tolerate 4-kV HBM ESD  
A0P  
D15  
D14  
10  
11  
A1M  
Packaged in Thin Shrink Small-Outline  
Package With 20 Mil Terminal Pitch  
A1P 12  
LVDSV  
13  
LVDSGND 14  
45 D13  
44 GND  
43 D12  
CC  
Consumes <1 mW When Disabled  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
A2M  
A2P  
D11  
D10  
Wide Phase-Lock Input Frequency Range  
20 MHz to 65 MHz  
CLKINM  
CLKINP  
A3M  
V
CC  
No External Components Required for PLL  
D9  
D8  
D7  
GND  
D6  
D5  
D4  
D3  
Meets or Exceeds the Requirements of  
ANSI EIA/TIA-644 Standard  
A3P  
Industrial Temperature Qualified  
LVDSGND  
PLLGND  
T = –40°C to 85°C  
A
Replacement for the DS90CR286  
PLLV  
CC  
PLLGND  
SHTDN  
CLKOUT  
D0  
description  
V
CC  
The SN65LVDS94 LVDS serdes (serializer/des-  
erializer) receiver contains four serial-in 7-bit  
parallel-out shift registers, a 7× clock synthesizer,  
and five low-voltage differential signaling (LVDS)  
line receivers in a single integrated circuit. These  
functions allow receipt of synchronous data from  
D2  
D1  
GND  
a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and  
expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate.  
When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the  
LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A  
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for  
the expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).  
The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control.  
The data bus appears the same at the input to the transmitter and output of the receiver with the data  
transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear  
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A  
low level on this signal clears all internal registers to a low level.  
The SN65LVDS94 is characterized for operation over ambient air temperatures of –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

中文翻译

下载PDF

SN65LVDS94DGG 替代型号

型号 品牌 替代类型 描述 数据表
DS90CR286MTDX/NOPB TI

完全替代

 DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
SN65LVDS94DGGR TI

完全替代

 LVDS SERDES RECEIVER
SN65LVDS94DGGG4 TI

完全替代

 LVDS SERDES RECEIVER

与SN65LVDS94DGG相关器件

型号 品牌 获取价格 描述 数据表
SN65LVDS94DGGG4 TI

获取价格

 		LVDS SERDES RECEIVER
SN65LVDS94DGGR TI

获取价格

 		LVDS SERDES RECEIVER
SN65LVDS94DGGRG4 TI

获取价格

 		LVDS SERDES RECEIVER
SN65LVDS94IDGG TI

获取价格

 		5 LINE TRANSCEIVER, PDSO56
SN65LVDS94IDGGR TI

获取价格

 		5 LINE TRANSCEIVER, PDSO56
SN65LVDS95 TI

获取价格

 		LVDS SERDES TRANSMITTER
SN65LVDS95DGG TI

获取价格

 		LVDS SERDES TRANSMITTER
SN65LVDS95DGGG4 TI

获取价格

 		LVDS SERDES TRANSMITTER
SN65LVDS95DGGR TI

获取价格

 		LVDS SERDES TRANSMITTER
SN65LVDS95DGGREP TI

获取价格

 		LVDS SERDES TRANSMITTER

与SN65LVDS94DGG相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证