SN65LVDS94
LVDS SERDES RECEIVER
SLLS298E – MAY 1998 – REVISED FEBRUARY 2000
DGG PACKAGE
(TOP VIEW)
4:28 Data Channel Expansion at up to
1.820 Gigabits per Second Throughput
Suited for Point-to-Point Subsystem
Communication With Very Low EMI
D22
D23
V
CC
1
56
55
54
53
52
51
50
49
48
47
46
D21
D20
D19
GND
D18
D17
D16
2
4 Data Channels and Clock Low-Voltage
Differential Channels in and 28 Data and
Clock Out Low-Voltage TTL Channels Out
D24
3
GND
4
D25
5
Operates From a Single 3.3-V Supply and
250 mW (Typ)
D26
6
D27
7
LVDSGND
A0M
5-V Tolerant SHTDN Input
8
V
9
CC
Rising Clock Edge Triggered Outputs
Bus Pins Tolerate 4-kV HBM ESD
A0P
D15
D14
10
11
A1M
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
A1P 12
LVDSV
13
LVDSGND 14
45 D13
44 GND
43 D12
CC
Consumes <1 mW When Disabled
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A2M
A2P
D11
D10
Wide Phase-Lock Input Frequency Range
20 MHz to 65 MHz
CLKINM
CLKINP
A3M
V
CC
No External Components Required for PLL
D9
D8
D7
GND
D6
D5
D4
D3
Meets or Exceeds the Requirements of
ANSI EIA/TIA-644 Standard
A3P
Industrial Temperature Qualified
LVDSGND
PLLGND
T = –40°C to 85°C
A
Replacement for the DS90CR286
PLLV
CC
PLLGND
SHTDN
CLKOUT
D0
description
V
CC
The SN65LVDS94 LVDS serdes (serializer/des-
erializer) receiver contains four serial-in 7-bit
parallel-out shift registers, a 7× clock synthesizer,
and five low-voltage differential signaling (LVDS)
line receivers in a single integrated circuit. These
functions allow receipt of synchronous data from
D2
D1
GND
a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and
expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the
LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for
the expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).
The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A
low level on this signal clears all internal registers to a low level.
The SN65LVDS94 is characterized for operation over ambient air temperatures of –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265