SN65LVDS93
LVDS SERDES TRANSMITTER
SLLS302F – MAY 1998 – REVISED FEBRUARY 2000
DGG PACKAGE
(TOP VIEW)
28:4 Data Channel Compression at up to
1.82 Gigabits per Second Throughput
Suited for Point-to-Point Subsystem
Communication With Very Low EMI
V
D4
1
56
55
54
53
52
51
50
49
48
47
46
CC
D5
D3
2
28 Data Channels Plus Clock in
Low-Voltage TTL and 4 Data Channels Plus
Clock Out Low-Voltage Differential
D6
D7
D2
3
GND
D1
4
GND
D8
5
Selectable Rising or Falling Clock Edge
Triggered Inputs
D0
6
D9
D27
LVDSGND
Y1M
Y1P
Y2M
7
D10
Bus Pins Tolerate 6-kV HBM ESD
8
V
9
CC
Operates From a Single 3.3-V Supply and
250 mW (Typ)
D11
D12
10
11
5-V Tolerant Data Inputs
D13 12
GND 13
D14 14
45 Y2P
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
44 LVDSV
CC
43 LVDSGND
Consumes <1 mW When Disabled
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
D15
D16
Y3M
Wide Phase-Lock Input Frequency Range
20 MHz to 65 MHz
Y3P
CLKSEL
D17
CLKOUTM
CLKOUTP
Y4M
No External Components Required for PLL
D18
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
D19
Y4P
GND
D20
LVDSGND
PLLGND
Industrial Temperature Qualified
T = –40°C to 85°C
A
D21
PLLV
CC
Replacement for the DS90CR285
D22
PLLGND
SHTDN
CLKIN
D26
D23
description
V
CC
D24
D25
The SN65LVDS93 LVDS serdes (serializer/des-
erializer) transmitter contains four 7-bit parallel-
load serial-out shift registers, a 7× clock
GND
synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These
functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair
conductors for receipt by a compatible receiver, such as the SN65LVDS94.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The
frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices.
The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The
frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS93 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s).
The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge
with a low-level input and the possible use of the shutdown/clear (SHTDN). SHTDN is an active-low input to
inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal
clears all internal registers at a low level.
The SN65LVDS93 is characterized for operation over ambient air temperatures of –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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