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SN65LVDS93DGG PDF预览

SN65LVDS93DGG

更新时间： 2024-09-29 22:36:59
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
14页 194K
描述
LVDS SERDES TRANSMITTER

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SN65LVDS93DGG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP56,.3,20针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.83差分输出：YES
驱动器位数：4高电平输入电流最大值：0.00002 A
输入特性：STANDARD接口集成电路类型：LINE DRIVER
接口标准：EIA-644; TIA-644JESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：14 mm
湿度敏感等级：2功能数量：4
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：DIFFERENTIAL
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：
座面最大高度：1.2 mm子类别：Line Driver or Receivers
最大压摆率：120 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
电源电压1-最大：3.6 V电源电压1-分钟：3 V
电源电压1-Nom：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED最大传输延迟：13.38 ns
宽度：6.1 mmBase Number Matches：1

SN65LVDS93DGG 数据手册

 浏览型号SN65LVDS93DGG的Datasheet PDF文件第2页浏览型号SN65LVDS93DGG的Datasheet PDF文件第3页浏览型号SN65LVDS93DGG的Datasheet PDF文件第4页浏览型号SN65LVDS93DGG的Datasheet PDF文件第5页浏览型号SN65LVDS93DGG的Datasheet PDF文件第6页浏览型号SN65LVDS93DGG的Datasheet PDF文件第7页 
SN65LVDS93  
LVDS SERDES TRANSMITTER  
SLLS302F – MAY 1998 – REVISED FEBRUARY 2000  
DGG PACKAGE  
(TOP VIEW)  
28:4 Data Channel Compression at up to  
1.82 Gigabits per Second Throughput  
Suited for Point-to-Point Subsystem  
Communication With Very Low EMI  
V
D4  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
CC  
D5  
D3  
2
28 Data Channels Plus Clock in  
Low-Voltage TTL and 4 Data Channels Plus  
Clock Out Low-Voltage Differential  
D6  
D7  
D2  
3
GND  
D1  
4
GND  
D8  
5
Selectable Rising or Falling Clock Edge  
Triggered Inputs  
D0  
6
D9  
D27  
LVDSGND  
Y1M  
Y1P  
Y2M  
7
D10  
Bus Pins Tolerate 6-kV HBM ESD  
8
V
9
CC  
Operates From a Single 3.3-V Supply and  
250 mW (Typ)  
D11  
D12  
10  
11  
5-V Tolerant Data Inputs  
D13 12  
GND 13  
D14 14  
45 Y2P  
Packaged in Thin Shrink Small-Outline  
Package With 20 Mil Terminal Pitch  
44 LVDSV  
CC  
43 LVDSGND  
Consumes <1 mW When Disabled  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
D15  
D16  
Y3M  
Wide Phase-Lock Input Frequency Range  
20 MHz to 65 MHz  
Y3P  
CLKSEL  
D17  
CLKOUTM  
CLKOUTP  
Y4M  
No External Components Required for PLL  
D18  
Outputs Meet or Exceed the Requirements  
of ANSI EIA/TIA-644 Standard  
D19  
Y4P  
GND  
D20  
LVDSGND  
PLLGND  
Industrial Temperature Qualified  
T = –40°C to 85°C  
A
D21  
PLLV  
CC  
Replacement for the DS90CR285  
D22  
PLLGND  
SHTDN  
CLKIN  
D26  
D23  
description  
V
CC  
D24  
D25  
The SN65LVDS93 LVDS serdes (serializer/des-  
erializer) transmitter contains four 7-bit parallel-  
load serial-out shift registers, a 7× clock  
GND  
synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These  
functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair  
conductors for receipt by a compatible receiver, such as the SN65LVDS94.  
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock  
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The  
frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices.  
The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The  
frequency of CLKOUT is the same as the input clock, CLKIN.  
The SN65LVDS93 requires no external components and little or no control. The data bus appears the same  
at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s).  
The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge  
with a low-level input and the possible use of the shutdown/clear (SHTDN). SHTDN is an active-low input to  
inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal  
clears all internal registers at a low level.  
The SN65LVDS93 is characterized for operation over ambient air temperatures of –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

中文翻译

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SN65LVDS93DGG 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS93DGGR TI

完全替代

 20MHz 至 68MHz LVDS 串行器/解串器变送器 | DGG | 56 | -4
SN65LVDS93DGGG4 TI

完全替代

 20MHz 至 68MHz LVDS 串行器/解串器变送器 | DGG | 56

与SN65LVDS93DGG相关器件

型号 品牌 获取价格 描述 数据表
SN65LVDS93DGGG4 TI

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 		20MHz 至 68MHz LVDS 串行器/解串器变送器 | DGG | 56
SN65LVDS93DGGR TI

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 		20MHz 至 68MHz LVDS 串行器/解串器变送器 | DGG | 56 | -4
SN65LVDS93IDGG TI

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 		5 LINE TRANSCEIVER, PDSO56
SN65LVDS93IDGGR TI

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 		5 LINE TRANSCEIVER, PDSO56
SN65LVDS94 TI

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 		LVDS SERDES RECEIVER
SN65LVDS94DGG TI

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 		LVDS SERDES RECEIVER
SN65LVDS94DGGG4 TI

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 		LVDS SERDES RECEIVER
SN65LVDS94DGGR TI

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 		LVDS SERDES RECEIVER
SN65LVDS94DGGRG4 TI

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 		LVDS SERDES RECEIVER
SN65LVDS94IDGG TI

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 		5 LINE TRANSCEIVER, PDSO56

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