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SN65LVDS93ADGG PDF预览

SN65LVDS93ADGG

更新时间： 2024-11-25 06:12:51
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
25页 675K
描述
FLATLINK TRANSMITTER

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SN65LVDS93ADGG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP56,.3,20针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.35差分输出：YES
驱动器位数：4高电平输入电流最大值：0.000025 A
输入特性：STANDARD接口集成电路类型：LINE DRIVER
接口标准：GENERAL PURPOSEJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：14 mm
湿度敏感等级：2功能数量：4
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C最小输出摆幅：0.25 V
输出特性：DIFFERENTIAL输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：116 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

SN65LVDS93ADGG 数据手册

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SN65LVDS93A  
www.ti.com................................................................................................................................................................................................. SLLS992 –AUGUST 2009  
FLATLINK™ TRANSMITTER  
Check for Samples: SN65LVDS93A  
1
FEATURES  
•
28 Data Channels Plus Clock In Low-Voltage  
TTL to 4 Data Channels Plus Clock Out  
Low-Voltage Differential  
2
•
Industrial Temperature Range –40°C to 85°C  
•
•
•
LVDS Display Serdes Interfaces Directly to  
LCD Display Panels with Integrated LVDS  
•
•
Consumes Less Than 1mW When Disabled  
Selectable Rising or Falling Clock Edge  
Triggered Inputs  
Package Options: 4.5mm × 7mm BGA, and  
8.1mm × 14mm TSSOP  
•
•
•
ESD: 5kV HBM  
1.8V up to 3.3V Tolerant Data Inputs to  
Connect Directly to Low-Power, Low-Voltage  
Application and Graphic Processors  
Support Spread Spectrum Clocking (SSC)  
Compatible with all OMAP ™ 2x, OMAP™3x,  
and DaVinci ™ Application Processors  
•
Transfer Rate up to 135Mpps (Mega Pixel Per  
Second); Pixel Clock Frequency Range 10MHz  
to 135MHz  
APPLICATIONS  
•
•
•
LCD Display Panel Driver  
UMPC and Netbook PC  
Digital Picture Frame  
•
•
Suited for Display Resolutions Ranging From  
HVGA up to HD With Low EMI  
Operates From a Single 3.3V Supply and  
170mW (typ.) at 75MHz  
DESCRIPTION  
The SN65LVDS93A LVDS serdes (serializer/deserializer) transmitter contains four 7-bit parallel load serial-out  
shift registers, a 7 × clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single  
integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over  
five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94.  
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock  
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The  
frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices.  
The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The  
frequency of CLKOUT is the same as the input clock, CLKIN.  
The SN65LVDS93A requires no external components and little or no control. The data bus appears the same at  
the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The  
only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a  
lowlevel input and the possible use of the shutdown/clear (SHTDN). SHTDN is an active-low input to inhibit the  
clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all  
internal registers at a low level.  
The SN65LVDS93A is characterized for operation over ambient air temperatures of –40°C to 85°C.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
OMAP, DaVinci are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
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SN65LVDS93ADGG 替代型号

型号 品牌 替代类型 描述 数据表
DS90C383BMTX/NOPB TI

类似代替

 +3.3V 可编程 LVDS 发送器 24 位平板显示器 (FPD) 链路 - 65MHz
SN75LVDS83ADGG TI

类似代替

 FLATLINK™ TRANSMITTER
SN75LVDS83DGG TI

类似代替

 FLATLINKE TRANSMITTER

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SN65LVDS93AIDGGRQ1 TI

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 		10MHz – 135MHz 28 位平板显示器链路 LVDS 串行解串器发送器 | DG
SN65LVDS93A-Q1 TI

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 		10MHz – 135MHz 28 位平板显示器链路 LVDS 串行解串器发送器
SN65LVDS93AZQLR TI

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SN65LVDS93B TI

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 		10MHz - 85MHz LVDS 串行器/解串器变送器
SN65LVDS93BDGG TI

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 		暂无描述
SN65LVDS93BDGGR TI

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 		10MHz - 85MHz LVDS 串行器/解串器变送器 | DGG | 56 | -4
SN65LVDS93BIDGGRQ1 TI

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 		10MHz - 85MHz 汽车类 28 位平板显示器链路 LVDS | DGG | 56
SN65LVDS93BIDGGTQ1 TI

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 		10MHz - 85MHz 汽车类 28 位平板显示器链路 LVDS | DGG | 56
SN65LVDS93B-Q1 TI

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 		10MHz - 85MHz 汽车类 28 位平板显示器链路 LVDS

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