Datasheet > 驱动程序和接口 > 线路驱动器或接收器> SN65LVDS93A

SN65LVDS93A

更新时间： 2024-09-30 06:12:51

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
25页	675K
描述
FLATLINK TRANSMITTER

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数据手册
替代型号

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SN65LVDS93A 数据手册

SN65LVDS93A

www.ti.com................................................................................................................................................................................................. SLLS992 –AUGUST 2009

FLATLINK™ TRANSMITTER

Check for Samples: SN65LVDS93A

FEATURES

•

28 Data Channels Plus Clock In Low-Voltage

TTL to 4 Data Channels Plus Clock Out

Low-Voltage Differential

•

Industrial Temperature Range –40°C to 85°C

•

LVDS Display Serdes Interfaces Directly to

LCD Display Panels with Integrated LVDS

•

Consumes Less Than 1mW When Disabled

Selectable Rising or Falling Clock Edge

Triggered Inputs

Package Options: 4.5mm × 7mm BGA, and

8.1mm × 14mm TSSOP

•

ESD: 5kV HBM

1.8V up to 3.3V Tolerant Data Inputs to

Connect Directly to Low-Power, Low-Voltage

Application and Graphic Processors

Support Spread Spectrum Clocking (SSC)

Compatible with all OMAP ™ 2x, OMAP™3x,

and DaVinci ™ Application Processors

•

Transfer Rate up to 135Mpps (Mega Pixel Per

Second); Pixel Clock Frequency Range 10MHz

to 135MHz

APPLICATIONS

•

LCD Display Panel Driver

UMPC and Netbook PC

Digital Picture Frame

•

Suited for Display Resolutions Ranging From

HVGA up to HD With Low EMI

Operates From a Single 3.3V Supply and

170mW (typ.) at 75MHz

DESCRIPTION

The SN65LVDS93A LVDS serdes (serializer/deserializer) transmitter contains four 7-bit parallel load serial-out

shift registers, a 7 × clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single

integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over

five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock

signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The

frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices.

The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The

frequency of CLKOUT is the same as the input clock, CLKIN.

The SN65LVDS93A requires no external components and little or no control. The data bus appears the same at

the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The

only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a

lowlevel input and the possible use of the shutdown/clear (SHTDN). SHTDN is an active-low input to inhibit the

clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all

internal registers at a low level.

The SN65LVDS93A is characterized for operation over ambient air temperatures of –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OMAP, DaVinci are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...25

中文翻译

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SN65LVDS93A 替代型号

型号	品牌	替代类型	描述	数据表
SN65LVDS93A-Q1	TI	功能相似	10MHz – 135MHz 28 位平板显示器链路 LVDS 串行解串器发送器
DS90CR285	TI	功能相似	+3.3V 上升沿数据选通 LVDS 28 位 Channel Link 发送器 - 66

与SN65LVDS93A相关器件

型号	品牌	获取价格	描述	数据表
SN65LVDS93ADGG	TI	获取价格	FLATLINK TRANSMITTER
SN65LVDS93ADGGR	TI	获取价格	FLATLINK TRANSMITTER
SN65LVDS93AIDGGRQ1	TI	获取价格	10MHz – 135MHz 28 位平板显示器链路 LVDS 串行解串器发送器 \| DG
SN65LVDS93A-Q1	TI	获取价格	10MHz – 135MHz 28 位平板显示器链路 LVDS 串行解串器发送器
SN65LVDS93AZQLR	TI	获取价格	FLATLINK TRANSMITTER
SN65LVDS93B	TI	获取价格	10MHz - 85MHz LVDS 串行器/解串器变送器
SN65LVDS93BDGG	TI	获取价格	暂无描述
SN65LVDS93BDGGR	TI	获取价格	10MHz - 85MHz LVDS 串行器/解串器变送器 \| DGG \| 56 \| -4
SN65LVDS93BIDGGRQ1	TI	获取价格	10MHz - 85MHz 汽车类 28 位平板显示器链路 LVDS \| DGG \| 56
SN65LVDS93BIDGGTQ1	TI	获取价格	10MHz - 85MHz 汽车类 28 位平板显示器链路 LVDS \| DGG \| 56

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