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Datasheet > 驱动程序和接口 > 线路驱动器或接收器> SN65LVDS86AQDGGRG4
SN65LVDS86AQDGGRG4 PDF预览

SN65LVDS86AQDGGRG4

更新时间： 2024-11-25 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
17页 162K
描述
FlatLink™ RECEIVER

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SN65LVDS86AQDGGRG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：0.50 MM PITCH, GREEN, PLASTIC, TSSOP-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：5.69Is Samacsys：N
差分输出：NO高电平输入电流最大值：0.000025 A
输入特性：DIFFERENTIAL接口集成电路类型：LINE RECEIVER
接口标准：EIA-644; TIA-644JESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
湿度敏感等级：2功能数量：1
端子数量：48最高工作温度：125 °C
最低工作温度：-40 °C输出特性：TOTEM-POLE
最大输出低电流：0.000025 A输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：7 ns接收器位数：3
筛选级别：AEC-Q100座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：40 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

SN65LVDS86AQDGGRG4 数据手册

 浏览型号SN65LVDS86AQDGGRG4的Datasheet PDF文件第2页浏览型号SN65LVDS86AQDGGRG4的Datasheet PDF文件第3页浏览型号SN65LVDS86AQDGGRG4的Datasheet PDF文件第4页浏览型号SN65LVDS86AQDGGRG4的Datasheet PDF文件第5页浏览型号SN65LVDS86AQDGGRG4的Datasheet PDF文件第6页浏览型号SN65LVDS86AQDGGRG4的Datasheet PDF文件第7页 
SN65LVDS86A-Q1  
www.ti.com  
SLLS768A –AUGUST 2006–REVISED JANUARY 2012  
FlatLink™ RECEIVER  
Check for Samples: SN65LVDS86A-Q1  
1
FEATURES  
DGG PACKAGE  
(TOP VIEW)  
2
•
3:21 Data Channel Expansion at up to  
178.5 Mbytes/s Throughput  
D17  
D18  
GND  
VCC  
D16  
D15  
D14  
GND  
D13  
VCC  
D12  
D11  
D10  
GND  
D9  
•
Suited for SVGA, XGA, or SXGA Display Data  
Transmission From Controller to Display With  
Very Low EMI  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
2
3
D19  
D20  
4
•
Three Data Channels and Clock Low-Voltage  
Differential Channels In and 21 Data and Clock  
Low-Voltage TTL Channels Out  
5
NC  
6
LVDSGND  
A0M  
7
•
•
•
Operates From a Single 3.3-V Supply  
8
Tolerates 4-kV Human-Body Model (HBM) ESD  
A0P  
A1M  
9
Packaged in Thin Shrink Small-Outline  
Package (TSSOP) With 20-Mil Terminal Pitch  
10  
11  
12  
A1P  
LVDSVCC  
•
•
Consumes Less Than 1 mW When Disabled  
Wide Phase-Lock Input Frequency Range  
31 MHz to 68 MHz  
LVDSGND 13  
36 VCC  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
A2M  
A2P  
D8  
D7  
•
•
No External Components Required for PLL  
CLKINM  
CLKINP  
LVDSGND  
PLLGND  
PLLVCC  
PLLGND  
SHTDN  
CLKOUT  
D0  
D6  
GND  
D5  
Inputs Meet or Exceed the Standard  
Requirements of ANSI EIA/TIA-644 Standard  
•
Improved Replacement for the SN75LVDS86  
and NSC DS90C364  
D4  
D3  
VCC  
D2  
•
•
Improved Jitter Tolerance  
Qualified for Automotive Applications  
D1  
GND  
NC − Not connected  
DESCRIPTION  
The SN65LVDS86A FlatLink™ receiver contains three serial-in 7-bit parallel-out shift registers and four  
low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt  
of synchronous data from a compatible transmitter, such as the SN75LVDS81, '83, '84, or '85, over four  
balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data at a  
lower transfer rate.  
When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input  
clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The  
SN65LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).  
The SN65LVDS86A requires only four line-termination resistors for the differential inputs and little or no control.  
The data bus appears the same at the input to the transmitter and output of the receiver with the data  
transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear  
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low  
level on this signal clears all internal registers to a low level.  
The SN65LVDS86A is characterized for operation over the full automotive temperature range of –40°C to 125°C.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
FlatLink is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006–2012, Texas Instruments Incorporated  
 
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